Method for producing 3D semiconductor devices and structures with transistors and memory cells

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming memory control circuits in and/or on said first level,
• wherein said memory control circuits comprise first single crystal transistors, and
• wherein said memory control circuits comprise at least two interconnection metal layers;
• forming at least one second level disposed above or below said memory control circuits;
• performing a first etch step into said at least one second level;
• forming at least one third level disposed on top of said second level;
• and
• performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
• wherein each of said plurality of first memory cells comprise at least one second transistor,
• wherein each of said plurality of second memory cells comprise at least one third transistor,
• wherein said additional processing steps comprise depositing a gate electrode simultaneously for said second transistors and said third transistors,
• wherein said gate electrode comprises tungsten,
• wherein said step of forming memory control circuits comprises an annealing step for dopant activation, and
• wherein said annealing is reduced to accommodate the upcoming annealing steps for said second level and third level.

A method for producing a 3D semiconductor device, the method comprising:

• providing a first level, said first level comprising a first single crystal layer;
• forming memory control circuits in and/or on said first level,
• wherein said memory control circuits comprise first single crystal transistors, and
• wherein said memory control circuits comprise at least two interconnection metal layers;
• forming at least one second level disposed above or below said memory control circuits;
• performing a first etch step into said at least one second level;
• forming at least one third level disposed on top of said second level;
• performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level,
• wherein each of said plurality of first memory cells comprise at least one second transistor,
• wherein each of said plurality of second memory cells comprise at least one third transistor;
• forming at least one via, said at least one via is disposed through said third level and through said second level, and connects to at least one of said at least two interconnection metal layers;
• and
• a step of gate replacement of said at least one third transistor.