Image sensor and camera module including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDaeyun Kim, Hoyong Lee
Life of this patent
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Abstract
An image sensor is disclosed. The image sensor includes: a demodulation clock generation circuit configured to generate M demodulation clock signals having N phases; a buffer circuit including M signal lines configured to transfer each of the M demodulation clock signals; and a pixel array including a plurality of pixels, wherein a pixel of the plurality of pixels has M taps and is configured to receive M demodulation signals passing through the M signal lines as inputs. Each of the M demodulation signals is conducted by each of the M signal lines during an integration time of one frame of the pixel, and M and N are integers greater than or equal to 2.
Claims20
An image sensor comprising:
- a demodulation clock generation circuit configured to generate M demodulation clock signals having N phases;
- a buffer circuit comprising M signal lines configured to transfer each of the M demodulation clock signals;
- and
- a pixel array comprising a plurality of pixels, wherein a pixel of the plurality of pixels has M taps and is configured to receive M demodulation signals passing through the M signal lines as inputs,
- wherein each of the M demodulation signals is conducted by each of the M signal lines during an integration time of one frame of the pixel, and
- wherein M and N are integers greater than or equal to 2.
An image sensor comprising:
- a demodulation clock generation circuit configured to generate a first demodulation clock signal having a first phase, a second demodulation clock signal having a second phase, a third demodulation clock signal having a third phase, and a fourth demodulation clock signal having a fourth phase;
- a buffer circuit comprising a first signal line, a second signal line, a third signal line, and a fourth signal line configured to transfer the first demodulation clock signal, the second demodulation clock signal, the third demodulation clock signal, and the fourth demodulation clock signal;
- and
- a pixel array comprising a plurality of pixels configured to receive a first tap signal, a second tap signal, a third tap signal, and a fourth tap signal passing through the first to fourth signal lines as inputs of a pixel, among the plurality of pixels, having four taps,
- wherein an integration time of one frame comprises a first section, a second section, a third section and a fourth section, and
- wherein the first tap signal passes through the first signal line in the first section, the second signal line in the second section, the third signal line in the third section, and the fourth signal line in the fourth section.
A camera module comprising:
- a light source configured to transmit a light signal to an object;
- and
- an image sensor configured to receive the light signal reflected from the object,
- wherein the image sensor comprises:
- a demodulation clock generation circuit configured to generate M demodulation clock signals having N phases;
- a buffer circuit comprising M signal lines configured to transfer each of the M demodulation clock signals;
- and
- a pixel array comprising a plurality of pixels, wherein a pixel of the plurality of pixels has M taps and is configured to receive M demodulation signals passing through the M signal lines as inputs,
- wherein each of the M demodulation signals is conducted by each of the M signal lines during an integration time of one frame of the pixel, and
- wherein M and N are integers greater than or equal to 2.
Dependencies are inferred from the claim text.