Burst-tolerant decision feedback equalization

An integrated-circuit memory control component (memory control IC) comprising:

• sampling circuitry to generate a sequence of read data bits by sampling a data signaling link during each of a corresponding sequence of data sampling intervals and resolving each of the read data bits to a logic state according to voltage levels, during the data sampling interval, of both the data signaling link and an equalization signal;
• and
• equalization circuitry to generate the equalization signal for each of the data sampling intervals based on either (i) the logic state of one or more previously generated read data bits or (ii) one or more bit values having predetermined logic states, depending on whether the data sampling interval is preceded by a time period in which no data is conveyed to the memory control IC via the data signaling link.

An integrated-circuit memory control component (memory control IC) comprising:

• means for sampling a data signaling link during each of a sequence of data sampling intervals to generate a corresponding sequence of read data bits, including resolving each of the read data bits to a logic state according to voltage levels, during the data sampling interval, of both the data signaling link and an equalization signal;
• and
• means for generating the equalization signal for each of the data sampling intervals based on either (i) the logic state of one or more previously generated read data bits or (ii) one or more bit values having predetermined logic states, depending on whether the data sampling interval is preceded by a time period in which no data is conveyed to the memory control IC via the signaling link.