Driver circuit for GaN FET solid state relay
AssigneeEfficient Power Conversion Corporation
InventorMichael A. de Rooij
Life of this patent
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Abstract
A driver circuit for a solid-state relay which includes a split power supply. The positive supply of the split power supply provides a voltage for application to the gate of a power FET for supplying power to a load. The negative supply of the split power supply provides a negative voltage for turning off a control transistor. The control transistor prevents the power FET from conducting power to the load when the driver circuit is turned off. The circuit is particularly adapted for driving a power GaN FET solid state relay. The circuit is provided in a cascaded embodiment to increase the blocking voltage of the solid-state relay.
Claims20
A driver circuit for a solid state relay, comprising:
- a main FET;
- a depletion mode control transistor;
- and
- a split power supply, wherein a positive supply of the split power supply provides a positive voltage applied to a gate of the main FET for supplying power to a load, and a negative supply of the split power supply provides a negative voltage for turning off the depletion mode control transistor, wherein the control transistor prevents the main FET from conducting power to the load when the driver circuit is turned off,
- wherein the driver circuit further comprises a first capacitor, a second capacitor, a first diode, and a second diode, wherein the first diode is configured to positively charge the first capacitor in response to the positive voltage, and the second diode is configured to negatively charge the second capacitor, which turns off the depletion mode control transistor.
Dependencies are inferred from the claim text.