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US 12,463,609 B2Granted
Dynamic amplifier with reduced sensitivity
AssigneeQUALCOMM Incorporated
InventorBehnam Sedighi
Life of this patent
Estimating the term…
Abstract
Techniques and apparatus for reducing sensitivity (e.g., less gain variation due to parasitic capacitance) in dynamic amplifiers. One example dynamic amplifier generally includes a pair of differential input transistors, a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier, a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, and a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes.
Claims20
A dynamic amplifier comprising:
- a pair of differential input nodes comprising a first input node and a second input node;
- a pair of differential output nodes comprising a first output node and a second output node;
- a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node;
- a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node;
- a first switch coupled between the first intermediate node and the first output node;
- a second switch coupled between the second intermediate node and the second output node;
- a third switch coupled between the first intermediate node and the second output node;
- a fourth switch coupled between the second intermediate node and the first output node;
- a fifth switch coupled between the first intermediate node and the second output node;
- and
- a sixth switch coupled between the second intermediate node and the first output node, wherein:
- for a first phase, the first switch, the second switch, the third switch, and the fourth switch are configured to be closed and the fifth switch and the sixth switch are configured to be open;
- and
- for a second phase subsequent to the first phase, the first switch and the second switch are configured to be open and the third switch, the fourth switch, the fifth switch, and the sixth switch are configured to be closed.
11 more elements
A dynamic amplifier comprising:
- a pair of differential input nodes comprising a first input node and a second input node;
- a pair of differential output nodes comprising a first output node and a second output node;
- a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node;
- a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node;
- a first switch coupled between the first intermediate node and the first output node;
- a second switch coupled between the second intermediate node and the second output node;
- a third switch coupled between the first intermediate node and the second output node;
- a fourth switch coupled between the second intermediate node and the first output node;
- a fifth switch coupled between the first intermediate node and the second output node;
- a sixth switch coupled between the second intermediate node and the first output node;
- a seventh switch coupled between the second output node and a power supply rail;
- an eighth switch coupled between the first output node and the power supply rail, wherein a control input of the seventh switch is coupled to a control input of the eighth switch;
- and
- a current sink coupled between a source of the first differential input transistor and a reference potential node, wherein the source of the first differential input transistor is coupled to a source of the second differential input transistor.
11 more elements
A method of amplifying with a dynamic amplifier comprising:
- a pair of differential input nodes comprising a first input node and a second input node;
- a pair of differential output nodes comprising a first output node and a second output node;
- a first differential input transistor having a gate coupled to the first input node and having a drain coupled to a first intermediate node;
- a second differential input transistor having a gate coupled to the second input node and having a drain coupled to a second intermediate node;
- a first switch coupled between the first intermediate node and the first output node;
- a second switch coupled between the second intermediate node and the second output node;
- a third switch coupled between the first intermediate node and the second output node;
- a fourth switch coupled between the second intermediate node and the first output node;
- a fifth switch coupled between the first intermediate node and the second output node;
- and
- a sixth switch coupled between the second intermediate node and the first output node, the method comprising:
- charging a common-source node of the first differential input transistor and the second differential input transistor during a first phase, the charging including closing the first switch, the second switch, the third switch, and the fourth switch, wherein the fifth switch and the sixth switch are open;
- and
- amplifying a voltage difference between a first input signal at the first input node and a second input signal at the second input node, during a second phase subsequent to the first phase, the amplifying including opening the first switch and the second switch and closing the fifth switch and the sixth switch, wherein the third switch and the fourth switch are closed during the second phase.
11 more elements
A dynamic amplifier comprising:
- a pair of differential input transistors;
- a pair of cross-coupled switches coupled between the pair of differential input transistors and a pair of differential output nodes for the dynamic amplifier;
- a first pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes;
- and
- a second pair of switches coupled between the pair of differential input transistors and the pair of differential output nodes, wherein:
- for a first phase, the pair of cross-coupled switches and the first pair of switches are configured to be closed and the second pair of switches are configured to be open;
- and
- for a second phase subsequent to the first phase, the pair of cross-coupled switches are configured to be open and the first pair of switches and the second pair of switches are configured to be closed.
5 more elements
Dependencies are inferred from the claim text.