Multi-chip device with gate redistribution structure

A power device package, comprising:

• a first power transistor chip having a control electrode, a first load electrode and a second load electrode;
• a second power transistor chip having a control electrode, a first load electrode and a second load electrode;
• a control package terminal electrically coupled to the control electrode of the first power transistor chip via a first wire bond connection and to the control electrode of the second power transistor chip via a second wire bond connection;
• a first package terminal electrically coupled to the first load electrode of the first power transistor chip and to the first load electrode of the second power transistor chip;
• and
• a second package terminal electrically coupled to the second load electrode of the first power transistor chip and/or the second load electrode of the second power transistor chip,
• wherein a length of the first wire bond connection is greater than a length of the second wire bond connection,
• wherein a cross-sectional area of the first wire bond connection is greater than a cross-sectional area of the second wire bond connection.