Packaging architectures for sub-terahertz radio frequency devices

An integrated circuit (IC) package, comprising:

• a first array of IC dies in a first layer, the first array of IC dies comprising an array of metal patches on a side opposite to a second layer;
• a second array of IC dies in the second layer between the first layer and a third layer;
• and
• a third array of IC dies in the third layer, wherein:
• the first array comprises radio frequency (RF) and analog circuitry,
• the IC dies in the first array, the second array and the third array comprise through-substrate vias (TSVs), and
• an interface between adjacent layers comprises interconnects having a pitch of 10 micrometers between adjacent ones of the interconnects.

A microelectronic assembly, comprising:

• a first IC die in a first layer, the first layer comprising an array of patch antennas on a side opposite to a second layer, wherein an individual patch antenna includes a stack of vertically stacked sublayers within the first layer, the sublayers separated from one another by a first dielectric and comprising a sublayer comprising a ground plane, a sublayer comprising a first metal patch, and a sublayer comprising a second metal patch;
• a second IC die in the second layer between the first layer and a third layer;
• and
• a third IC die in the third layer, wherein:
• the first IC die is part of an array of IC dies in the first layer,
• the second layer includes a second dielectric with through-dielectric vias (TDVs) surrounding the second IC die,
• the third layer includes a third dielectric with TDVs, and
• an interface between adjacent layers comprises interconnects having a pitch equal to or smaller than 10 micrometers between adjacent ones of the interconnects.