Memory structure, manufacturing method thereof, operating method thereof, and memory array

A manufacturing method of a memory structure, comprising:

• forming a first hole penetrating through a plurality of insulating layers and a plurality of first gate layers that are alternately stacked;
• forming a first dielectric layer to cover a sidewall of the first hole;
• forming a first doping layer in the first hole, wherein the first doping layer has a first conductive type;
• forming a second hole penetrating through the insulating layers and the first gate layers;
• partially removing the first gate layers exposed from the second hole to form a plurality of recess portions;
• forming a plurality of second dielectric layers in the recess portions;
• forming a plurality of second doping layers to cover the second dielectric layers, wherein the second doping layers have a second conductive type that is different from the first conductive type;
• forming a third dielectric layer in the second hole to cover the insulating layers and the second doping layers;
• forming a columnar channel in the second hole;
• removing the first dielectric layer, the first gate layers, and the second dielectric layers between the first doping layer and the second doping layers to form a plurality of trenches;
• and
• forming a plurality of third doping layers in the trenches to directly contact the first doping layer and connect to the second doping layers, wherein the third doping layers have the second conductive type.