Multi stage charge pump circuits and semiconductor memory devices including the same

A charge pump circuit of a semiconductor memory device, comprising:

• a first pumping stage including:
• a first pumping capacitor including a first end configured to receive a clock signal and a second end connected with a first node;
• and
• a second pumping capacitor including a first end configured to receive an inverse clock signal and a second end connected with a second node;
• a first transfer stage configured to transfer a voltage of the first node to a third node when the clock signal is at a high level or to transfer a voltage of the second node to a fourth node when the inverse clock signal is at the high level;
• a second pumping stage including:
• a third pumping capacitor including a first end connected with the third node and a second end connected with a fifth node;
• and
• a fourth pumping capacitor including a first end connected with the fourth node and a second end connected with a sixth node;
• a second transfer stage configured to transfer a voltage of the fifth node to an output node when the clock signal is at the high level or to transfer a voltage of the sixth node to the output node when the inverse clock signal is at the high level;
• a first sub-pumping circuit configured to control a voltage change timing of the second node and the sixth node and a level change timing of the clock signal based on the clock signal;
• and
• a second sub-pumping circuit configured to control a voltage change timing of the first node and the fifth node and a level change timing of the inverse clock signal based on the inverse clock signal,
• wherein, when the clock signal is at the high level, the first pumping capacitor and the third pumping capacitor are electrically connected in series to the output node and output, to the output node, an output voltage that corresponds to multiple times an input voltage applied to the first pumping stage and the second pumping stage, and
• wherein, when the inverse clock signal is at the high level, the second pumping capacitor and the fourth pumping capacitor are electrically connected in series to the output node and output, to the output node, the output voltage that corresponds to multiple times the input voltage.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a peripheral circuit configured to receive a clock signal, a first power supply voltage, and a second power supply voltage that is higher than the first power supply voltage from a source external to the peripheral circuit, and further configured to read/write data from/in the memory cell array based on the clock signal, the first power supply voltage, and the second power supply voltage;
• and
• a charge pump circuit configured to generate an internal voltage corresponding to multiple times the second power supply voltage,
• wherein the charge pump circuit includes:
• a first pumping stage including:
• a first pumping capacitor including a first end configured to receive the clock signal and a second end connected with a first node;
• and
• a second pumping capacitor including a first end configured to receive an inverse clock signal generated by the peripheral circuit and a second end connected with a second node;
• a first transfer stage configured to transfer a voltage of the first node to a third node when the clock signal is at a high level or to transfer a voltage of the second node to a fourth node when the inverse clock signal is at the high level;
• a second pumping stage including:
• a third pumping capacitor including a first end connected with the third node and a second end connected with a fifth node;
• and
• a fourth pumping capacitor including a first end connected with the fourth node and a second end connected with a sixth node;
• and
• a second transfer stage configured to transfer a voltage of the fifth node to an output node when the clock signal is at the high level or to transfer a voltage of the sixth node to the output node when the inverse clock signal is at the high level,
• wherein, when the clock signal is at the high level, the first pumping capacitor and the third pumping capacitor are electrically connected in series to the output node and output, to the output node, an output voltage that corresponds to multiple times the second power supply voltage applied to the first pumping stage and the second pumping stage, and
• wherein, when the inverse clock signal is at the high level, the second pumping capacitor and the fourth pumping capacitor are electrically connected in series to the output node and output, to the output node, the output voltage that corresponds to multiple times the second power supply voltage.