Low latency synchronization

An integrated circuit, comprising:

• an input operable to receive an input pulse signal from a first clock domain;
• an output operable to provide an output pulse signal in a second clock domain;
• a first flip-flop having a first stage input, a first clock input, and a first stage output, wherein the first clock input is driven by a first clock signal of the first clock domain, and the first stage input is driven by a result of XOR-ing the input pulse signal and the first stage output;
• and
• a second flip-flop having a second stage input, a second clock input, and a second stage output, wherein the second clock input is driven by a second clock signal of the second clock domain, and the second stage input is driven by the first stage output,
• wherein the output pulse signal is generated by XOR-ing the second stage output with the first stage output, and
• wherein the first clock signal has a first frequency that is obtained by applying a scaling factor to a second frequency of the second clock signal, and the first clock signal and the second clock signal are based on a same clock source.