Stacked dies for machine learning accelerator

A method, comprising:

• executing a shader program on an accelerated processing device (“APD”) core die;
• in accordance with instructions of the shader program, directing a set of machine learning (“ML”) arithmetic logic units (“ALUs”) of an ML accelerator die to perform a set of machine learning tasks, via one or more inter-die interconnects, wherein the ML accelerator die includes a memory, wherein the ML accelerator die is stacked with the APD core die, wherein the ML accelerator die includes one or more machine learning accelerators, and wherein each machine learning accelerator is coupled to a local memory portion, to each other machine learning accelerator via a memory interconnect, and to the APD core die via an inter-die interconnect,;
• performing the set of machine learning tasks with ML ALUs;
• and
• configuring the memory as both a cache and a directly accessible memory, wherein the cache is configured to perform caching operations for the APD core die and the directly accessible memory is configured to perform memory operations for the machine learning die, wherein the memory includes a portion configured to switch between being used as a cache and being used as a directly accessible memory, wherein the switching comprises altering how much of the memory is used as the cache based on a specified amount.

A device, comprising:

• a processor;
• and
• an accelerated processing device (“APD”) including:
• a machine learning die including a memory and one or more machine learning accelerators;
• and
• a processing core die stacked with the machine learning die, the processing core die being configured to execute shader programs for controlling operations on the machine learning die, one or more of the shader programs being specified by the processor,
• wherein each machine learning accelerator is coupled to a local memory portion, to each other machine learning accelerator via a memory interconnect, and to the processing core die via an inter-die interconnect,
• wherein the memory is configurable as including both a cache and a directly accessible memory,
• wherein the memory includes a portion configured to switch between being used as a cache and being used as a directly accessible memory, wherein the switching comprises altering how much of the memory is used as the cache based on a specified amount;
• and
• wherein the cache is configured to perform caching operations for the processing core die and the directly accessible memory is configured to perform memory operations for the machine learning die.