Radiation induced error detection in solid-state devices

A method for detecting radiation induced errors in a solid-state device, the method comprising:

• receiving an ionizing radiation in a substrate of the solid-state device;
• performing a plurality of logic functions with a plurality of logic circuits, wherein the plurality of logic circuits are:
• located in an area on the substrate;
• and
• individually susceptible to a corruption due to the ionizing radiation;
• initializing each of a plurality of integrity cells to a predetermined state, wherein the plurality of integrity cells are:
• located in the area on the substrate;
• arranged in a pattern such that a respective subset of logic circuits, in the plurality of logic circuits, surrounds each integrity cell of the plurality of integrity cells;
• and
• individually susceptible to disruption of the predetermined state in response to the ionizing radiation;
• reading the plurality of integrity cells via a collection circuit that includes sampling circuitry located on the substrate;
• asserting, via the collection circuit, a report signal to an error detection and correction circuit located on the substrate, wherein the report signal identifies the corruption in a subset of logic circuits in the plurality of logic circuits due to the ionizing radiation in response to reading an incorrect bit in an integrity cell, of the plurality of integrity cells, that is surrounded by the subset of logic circuits;
• and
• resetting, via the collection circuit, the integrity cell to the predetermined state in response to reading the incorrect bit.

A solid-state device comprising:

• a substrate that receives an ionizing radiation;
• a plurality of logic circuits operational to perform a plurality of logic functions, wherein the plurality of logic circuits are:
• located in an area on the substrate;
• and
• individually susceptible to the ionizing radiation;
• a plurality of integrity cells that are:
• located in the area on the substrate;
• arranged in a pattern such that a respective subset of logic circuits, in the plurality of logic circuits, surrounds each integrity cell of the plurality of integrity cells;
• and
• voltage biased relative to the plurality of logic circuits to establish a plurality of electric fields, wherein the plurality of electric fields direct a plurality of ions created by the ionizing radiation away from the plurality of logic circuits;
• an error detection and correction circuit located on the substrate;
• and
• a collection circuit comprising sampling circuitry located on the substrate, wherein the sampling circuitry is operational to cause the collection circuit to:
• read the plurality of integrity cells;
• assert a report signal to the error detection and correction circuit, wherein the report signal identifies a corruption in a subset of logic circuits in the plurality of logic circuits due to the ionizing radiation in response to reading an incorrect bit in an integrity cell, of the plurality of integrity cells, that is surrounded by the subset of logic circuits;
• and
• reset the integrity cell to a predetermined state in response to reading the incorrect bit.