US 12,461,748 B1Granted

Method and apparatus for encoding of processor instruction set

AssigneeCadence Design Systems, Inc.

InventorsRong Chen, He Xiao, Nenad Nedeljkovi, Dan Nicolaescu, James Kim, Jiayuan Chen

Life of this patent

Estimating the term…

Loading patent…

Abstract

An approach of the present disclosure includes an algorithm to encode an instruction set of a domain-specific processor automatically in an optimal way, and which yields area-effective hardware. Instruction operands and opcodes can be encoded separately or at the same time. Instructions are not encoded one by one but can be encoded in groups, and instructions are grouped automatically. The decoding logic of control signals for each group of instructions, such as register read enable and write enable, is fed to a logic minimizer to obtain an encoding constraint matrix, and the encoding of each instruction in each instruction group is done using an optimal state assignment method.

Claims20

Dependent claims

A method to encode an instruction set of a domain-specific processor, wherein the encoded instruction set is used by a compiler to generate object code for execution by the domain-specific processor, the method comprising:

identifying a set of instructions for the domain-specific processor, wherein the set of instructions include a core set of instructions for execution by a core instruction set architecture of the domain-specific processor and an extended set of instructions for execution by extended hardware of the domain-specific processor, and wherein the extended set of instructions and extended hardware are generated by an instruction extension generator in response to instruction designs provided for a target application of the domain-specific processor;
and
processing the identified set of instructions, including both the core set of instructions and the extended set of instructions, so as to generate the encoded instruction set for the domain-specific processor, wherein the encoded instruction set comprises an encoded opcode and an encoded operand for each instruction of the identified set of instructions, and wherein the encoded opcode of each instruction contains the same number of opcode bits and wherein the encoded operand of each instruction contains the same number of operand bits, the processing including:
determining the same number of opcode bits and the same number of operand bits;
automatically encoding operands for the identified set of instructions such that each instruction of the identified set of instructions is assigned a set of operand bits for all possible operands for the each instruction;
and
automatically encoding opcodes for the identified set of instructions such that each instruction of the identified set of instructions is assigned a unique sequence of opcode bits.

4 more elements

A system for configuring a domain-specific processor, comprising:

a memory for storing a set of instructions that have been prepared for the domain-specific processor;
and
an instruction encoding module configured to:
identify the set of instructions for the domain-specific processor, wherein the set of instructions include a core set of instructions for execution by a core instruction set architecture of the domain-specific processor and an extended set of instructions for execution by extended hardware of the domain-specific processor, and wherein the extended set of instructions and extended hardware are generated by an instruction extension generator in response to instruction designs provided for a target application of the domain-specific processor;
and
process the set of instructions, including both the core set of instructions and the extended set of instructions, so as to generate an encoded instruction set for the domain-specific processor,
wherein the encoded instruction set is used by a compiler to generate object code for execution by the domain-specific processor, and
wherein the encoded instruction set comprises an encoded opcode and an encoded operand for each instruction of the identified set of instructions, and wherein the encoded opcode of each instruction contains the same number of opcode bits and wherein the encoded operand of each instruction contains the same number of operand bits, and
wherein the instruction encoding module is further configured to:
determine the same number of opcode bits and the same number of operand bits;
automatically encode operands for the identified set of instructions such that each instruction of the identified set of instructions is assigned a set of operand bits for all possible operands for the each instruction;
and
automatically encode opcodes for the identified set of instructions such that each instruction of the identified set of instructions is assigned a unique sequence of opcode bits.

10 more elements

A computer program product comprising non-transitory computer readable media storing instructions which, when executed by a processor, cause the processor to perform method to encode an instruction set of a domain-specific processor, wherein the encoded instruction set is used by a compiler to generate object code for execution by the domain-specific processor, the method comprising:

identifying a set of instructions for the domain-specific processor, wherein the set of instructions include a core set of instructions for execution by a core instruction set architecture of the domain-specific processor and an extended set of instructions for execution by extended hardware of the domain-specific processor, and wherein the extended set of instructions and extended hardware are generated by an instruction extension generator in response to instruction designs provided for a target application of the domain-specific processor;
and
processing the identified set of instructions, including both the core set of instructions and the extended set of instructions, so as to generate the encoded instruction set for the domain-specific processor, wherein the encoded instruction set comprises an encoded opcode and an encoded operand for each instruction of the identified set of instructions, and wherein the encoded opcode of each instruction contains the same number of opcode bits and wherein the encoded operand of each instruction contains the same number of operand bits, the processing including:
determining the same number of opcode bits and the same number of operand bits;
automatically encoding operands for the identified set of instructions such that each instruction of the identified set of instructions is assigned a set of operand bits for all possible operands for the each instruction;
and
automatically encoding opcodes for the identified set of instructions such that each instruction of the identified set of instructions is assigned a unique sequence of opcode bits.

4 more elements

Dependencies are inferred from the claim text.