MAC processing pipelines, circuitry to configure same, and methods of operating same

An integrated circuit comprising:

• a plurality MAC processors, interconnected into a linear pipeline, configurable to process input data during a plurality of execution cycles of an execution sequence, wherein each MAC processor of the plurality of the MAC processors includes:
• a multiplier circuit to (i) receive first input data at a first input and (ii) receive multiplier weight data at a second input, (iii) multiply first input data by multiplier weight data to generate product data, and (iv) output the product data,
• an accumulator circuit, coupled to the multiplier circuit of the associated MAC processor, to (i) receive accumulation data at a first input, (ii) receive the product data output by the associated multiplier circuit, (iii) add the accumulation data and the product data output by the associated multiplier circuit to generate second accumulation data, and (iv) output the second accumulation data via an output of the accumulation circuit, and
• an accumulation data path to couple the output of the accumulation circuit of the associated MAC processor to the first input thereof;
• a plurality of rotate input data paths, wherein each rotate input data path couples two sequential MAC processors of the linear pipeline including the first input of the multiplier circuit of a first MAC processor of sequential MAC processors to the first input of the multiplier circuit of the immediately following MAC processor of the associated sequential MAC processors of the linear pipeline;
• a plurality of rotate accumulation data paths, wherein each rotate accumulation data path couples two sequential MAC processors of the linear pipeline including the output of the accumulator circuit of a first MAC processor of sequential MAC processors to the first input of the accumulator circuit of the immediately following MAC processor of the associated sequential MAC processors of the linear pipeline;
• wherein each rotate input data path is configurable to provide rotate input data from a first MAC processor of sequential MAC processors to the immediately following MAC processor of the associated sequential MAC processors thereby forming a first configurable serial circular path, including the plurality of MAC processors of the linear pipeline, via the plurality of rotate input data paths;
• and
• wherein each rotate accumulation data path is configurable to provide rotate accumulation data from the first MAC processor of sequential MAC processors to the immediately following MAC processor of the associated sequential MAC processors thereby forming a second configurable serial circular path, including the plurality of MAC processors of the linear pipeline, via the plurality of rotate accumulation data paths.