In-memory near-data approximate acceleration

A method comprising:

• receiving, by an arithmetic unit and from a memory bank of a plurality of memory banks, one or more inputs, wherein the arithmetic unit and the memory bank are both disposed within a random access memory configured for parallel operation of multiple arithmetic units, wherein the plurality of memory banks comprise four bank-groups each with four of the memory banks, wherein each of the memory banks comprises two half-banks, and wherein a group of four arithmetic units from a plurality of arithmetic units is dedicated to two pairs of the two half-banks;
• performing, by the arithmetic unit, operations on the one or more inputs;
• providing, by the arithmetic unit, a result of the operations;
• and
• storing, in the memory bank, an output based on the result.

A system comprising:

• a processor;
• and
• a random access memory including:
• (i) a memory bank of a plurality of memory banks, wherein the plurality of memory banks comprise four bank-groups each with four of the memory banks, and (ii) a plurality of arithmetic units, each associated with one or more of the memory banks, wherein the arithmetic units are configured to perform operations on respective inputs and to provide respective results of the operations, wherein each of the memory banks comprises two half-banks, wherein a group of four arithmetic units from the plurality of arithmetic units is dedicated to two pairs of the two half-banks, and wherein the arithmetic units are configured for parallel operation;
• and (iii) a memory controller configured to receive instructions, from the processor, regarding locations within the memory bank from which to obtain the respective inputs and in which to write respective outputs based on the respective results.

A random access memory comprising:

• a plurality of memory banks;
• a plurality of arithmetic units, each associated with one or more of the memory banks, wherein the arithmetic units are configured to perform operations on respective inputs and to provide respective results of the operations, and wherein the arithmetic units are configured for parallel operation;
• and
• a memory controller configured to receive instructions, from a processor, regarding locations within the memory banks from which to obtain the respective inputs or in which to write respective outputs based on the respective results, wherein the respective inputs each include two or more inputs, wherein a first input of the two or more inputs is represented as a series of shift amounts based on a jth leading one of the first input, and wherein a second input of the two or more inputs is a multiplicand, and wherein performing the operations comprises:
• initializing a cumulative sum register to be zero;
• and
• for each respective shift amount of the shift amounts, (i) bitwise shifting left the multiplicand by the respective shift amount, and (ii) adding the multiplicand as shifted to the cumulative sum register.

A random access memory comprising:

• a plurality of memory banks;
• a plurality of arithmetic units, each associated with one or more of the memory banks, wherein the arithmetic units are configured to perform operations on respective inputs and to provide respective results of the operations, and wherein the arithmetic units are configured for parallel operation;
• and
• a memory controller configured to receive instructions, from a processor, regarding locations within the memory banks from which to obtain the respective inputs or in which to write respective outputs based on the respective results, wherein the respective inputs each include two or more inputs, wherein the instructions include a first instruction that causes the memory controller to read a first memory region containing configuration data for the arithmetic units, wherein the configuration data includes a first input of the two or more inputs, wherein the instructions include a second instruction that causes the memory controller to read a second memory region containing operands for the arithmetic units as configured by the configuration data, wherein the operands include a second input of the two or more inputs, and wherein the instructions include a third instruction that causes the memory controller to write the respective outputs to a third memory region.