Integrated circuit margin measurement

A semiconductor Integrated Circuit (IC), comprising:

• logic circuitry, defining a plurality of data paths and/or control logic circuits having a common clock;
• a device for failure risk measurement, comprising:
• a plurality of data-change pulse generators, each configured to receive a signal from a respective one of the plurality of data paths and/or control logic circuits and to generate a pulse on a respective output path when the received signal changes;
• a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;
• an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby;
• and
• a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.

A method for failure risk measurement in a semiconductor Integrated Circuit (IC), the method comprising:

• for each of a plurality of data paths and/or control logic circuits of the semiconductor IC, generating a pulse of a preset time duration on a respective output path when a signal from the respective data path and/or control logic circuit of the semiconductor IC changes, the plurality of data paths and/or control logic circuits of the semiconductor IC having a common clock;
• combining the output paths from the plurality of data-change pulse generators, to provide a combined output path thereby;
• delaying a signal on the combined output path by a configurable time duration, to provide a delayed combined output path signal thereby;
• and
• outputting a failure risk measurement signal from a device state element that is clocked by a signal based on the common clock, the delayed combined output path signal being received at a data input of the device state element.

A non-transitory computer readable medium having stored thereon a computer-readable encoding of a device for failure risk measurement in a semiconductor Integrated Circuit (IC), the computer-readable encoding of the loopback testing system comprising encodings of:

• a plurality of data-change pulse generators, each data-change pulse generator being configured, when a signal from a respective data path and/or control logic circuit of the semiconductor IC changes, to generate a pulse of a preset time duration on a respective output path, each of the data paths and/or control logic circuits of the semiconductor IC having a common clock;
• a signal combiner, configured to combine the output paths from the plurality of data-change pulse generators and provide a combined output path thereby;
• an adjustable delay circuit, configured to delay a signal on the combined output path by a configurable time duration, providing a delayed combined output path signal thereby;
• and
• a device state element, configured to receive the delayed combined output path signal at a data input, to be clocked by a signal based on the common clock and to output a failure risk measurement signal.