Identifying failures in device cores

A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising:

• channels for connecting to a number of pins on the DUT, the channels for sending test data to the DUT and for receiving measurement data from the DUT based on the test data;
• wherein the measurement data comprises time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream, where each data packet comprises a first number of bits from the first core and a second number of bits from the second core, where the data packets are transmitted in time slots with each time slot corresponding to transmission of the bitstream on the number of pins, and where the TDM data is repeated in a pattern on the channels every predetermined number of time slots;
• and
• circuitry associated with the channels to compare the measurement data with expected data, and to determine fail counts per core based on the comparison, with a fail count indicating how many times that the first core or the second core has failed a test;
• wherein the circuitry is configured to limit storage of subsequently-received measurement data for the first core or for the second core when the fail count exceeds a threshold number for the first core or the second core.

A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising:

• channels for connecting to a number of pins on the DUT, the channels for sending test data to the DUT and for receiving measurement data from the DUT based on the test data;
• wherein the measurement data comprises time-division-multiplexed (TDM) data comprised of successive data packets received from the DUT over the channels as part of a bitstream, where each data packet comprises a first number of bits from the first core and a second number of bits from the second core, where the data packets are transmitted in time slots with each time slot corresponding to a transmission of the bitstream on the number of pins, and where the TDM data is repeated in a pattern on the channels every predetermined number of time slots, and where each of the channels is configured to transmit data from both the first core and the second core;
• and
• circuitry associated with the channels to mask data from the first core or the second core based on user input, where masking comprises not storing, in memory, data from one of the channels for a selected one of the first core or the second core and storing data from the one of the channels for a non-selected one of the first core or the second core.