Transistor structure with multiple halo implants having epitaxial layer, high-k dielectric and metal gate

A method, comprising:

• forming a first gate mask on a surface of a substrate, the first gate mask having a length that is greater than a target n-type transistor channel length;
• forming a second gate mask on a surface of the substrate, the second gate mask having a length that is greater than a target p-type transistor channel length;
• ion implanting n-type dopants at a first energy with the first gate mask serving as an ion implantation mask to form first n-type halo regions in n-type transistor regions;
• ion implanting p-type dopants at a second energy with the second gate mask serving as an ion implantation mask to form first p-type halo regions in p-type transistor regions;
• forming first spacers on sides of the first and second gate masks;
• ion implanting first conductivity type dopants at a third energy with the first gate mask and first spacers serving as an ion implantation mask to form second n-type halo regions in n-type transistor regions, the third second energy being greater than the first energy;
• ion implanting second conductivity type dopants at a fourth energy with the second gate mask and second spacers serving as an ion implantation mask to form second p-type halo regions in p-type transistor regions, the fourth energy being greater than the second energy;
• forming an epitaxial layer over the surface including over the n-type and p-type transistor regions;
• forming insulating trenches in the substrate between the n-type and p-type transistor regions;
• forming a first insulator layer over the n-type and p-type transistor regions;
• forming a first dummy gate mask on a surface of the substrate, the first dummy gate mask having a length that is a target n-type transistor channel length;
• forming a second dummy gate mask on a surface of the substrate, the second dummy gate mask having a length that is a target p-type transistor channel length;
• ion implanting second conductivity type dopants at a fifth energy with the first dummy gate mask serving as an ion implantation mask to form n-type source-drain extensions in n-type transistor regions, the fifth energy being less than the third energy;
• ion implanting first conductivity type dopants at a sixth energy with the second dummy gate mask serving as an ion implantation mask to form p-type source-drain extensions in p-type transistor regions, the sixth energy being less than the fourth energy;
• forming second spacers on sides of the first and second dummy gate masks;
• ion implanting second conductivity type dopants at a seventh energy with the first dummy gate mask and second spacers serving as an ion implantation mask to form n-type source and drain regions in n-type transistor regions, the seventh energy being greater than the fifth energy;
• ion implanting first conductivity type dopants at an eighth energy with the second dummy gate mask and second spacers serving as an ion implantation mask to form p-type source and drain regions in p-type transistor regions, the eighth energy being greater than the sixth energy;
• forming a surface dielectric layer over the n-type and p-type transistor regions;
• planarizing the surface dielectric layer to expose a top surface of the first and second dummy gate masks;
• removing the first and second dummy gate masks to create first and second gate openings, respectively, between the second spacers;
• forming a high-permittivity (hi-K) insulator layer within at least the first and second gate openings, the hi-K insulator layer having a higher permittivity than silicon dioxide;
• forming at least a first work function metal gate layer within the first gate opening over the hi-K insulator layer having a first work function value;
• and
• forming at least a second work function metal gate layer within the second gate opening over the hi-K insulator layer having a second work function value.