US 12,457,683 B2 · Eddy current mitigation for on-chip inductors

Abstract

An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.

Claims20

Dependent claims

Circuitry comprising:

a substrate;
an inductor layered on the substrate, wherein the inductor comprises a loop that laterally surrounds a first region of the substrate;
a ring of ground traces on the substrate and extending around the inductor and a second region of the substrate, the ring of ground traces being laterally separated from the inductor by the second region of the substrate;
first capacitors layered on the substrate and overlapping the second region of the substrate;
and
second capacitors layered on the substrate and overlapping the first region of the substrate.

3 more elements

Dependencies are inferred from the claim text.

Eddy current mitigation for on-chip inductors

Life of this patent

Eddy current mitigation for on-chip inductors

Life of this patent

Abstract

Claims20