Noise filtering circuit, D/A converter, and electronic device including the same

A semiconductor device comprising:

• a bias voltage generating circuit configured to generate a bias voltage;
• a noise filtering circuit configured to filter noise of the bias voltage to generate a bias output voltage;
• and
• an output circuit configured to generate a regulated voltage using the bias output voltage,
• wherein the noise filtering circuit includes:
• a first amplifier configured to compensate for a difference between the bias voltage and the bias output voltage;
• a first transistor connected to an output of the first amplifier;
• a first capacitor connected to the first transistor;
• a second capacitor connected to an output of the first amplifier;
• a second transistor connected to the second capacitor and an input terminal of the first amplifier;
• and
• a second amplifier configured to receive the bias output voltage and provide an output to the second transistor based on the bias output voltage.

A memory device comprising:

• a bias voltage generating circuit configured to generate a bias voltage;
• a noise filtering circuit configured to filter noise of the bias voltage to generate a bias output voltage;
• a compensation circuit configured to receive the bias output voltage and provide a compensation current based on the bias output voltage;
• a memory cell;
• and
• a clamping circuit connected to the memory cell and compensation circuit and including a sensing node receiving the compensation current,
• wherein the noise filtering circuit includes:
• a first amplifier configured to compensate for a difference between the bias voltage and the bias output voltage;
• a first transistor connected to an output of the first amplifier;
• a first capacitor connected to the first transistor;
• a second capacitor connected to an output of the first amplifier;
• a second transistor connected to the second capacitor and an input terminal of the first amplifier;
• and
• a second amplifier configured to receive the bias output voltage and provide an output to the second transistor based on the bias output voltage.