Memory device and methods of erasure operation using different float times for string selection transistors

A memory system, comprising:

• a memory configured to store data, the memory comprising:
• a memory array, the memory array comprising a block and a first selection line,
• the block comprising a plurality of strings, each string comprising a first selection transistor, the first selection line being coupled to the first selection transistor;
• and
• a peripheral circuit, the peripheral circuit being coupled to the first selection line and being configured to perform an erase operation on the plurality of strings in the block, and
• a controller coupled to the memory and configured to control the memory,
• wherein to perform the erase operation, the peripheral circuit is configured to:
• at a first moment, float a first selection line coupled to a first selection transistor of a first string, the first string being a string that has been erased among the plurality of strings;
• and
• at a second moment after the first moment, float a first selection line coupled to a first selection transistor of a second string, the second string being a string that has not been erased among the plurality of strings.

A method of operating a memory, wherein the memory comprises a memory array, the memory array comprises a block and a first selection line, the block comprises a plurality of strings, and each string comprises a first selection transistor;

• wherein the method comprises performing an erase operation on the plurality of strings in the block, and the erase operation comprises:
• at a first moment, floating a first selection line coupled to a first selection transistor of a first string, the first string being a string that has been erased among the plurality of strings;
• and
• at a second moment after the first moment, floating a first selection line coupled to a first selection transistor of a second string, the second string being a string that has not been erased among the plurality of strings.