Programmable signal processing apparatus

A programmable signal processing apparatus comprising:

• a plurality of arithmetic logic units (ALUs);
• a CPU;
• and
• a memory that stores a program that, when executed by the CPU, causes the programmable signal processing apparatus to function as:
• a control unit configured to set settings for configuring a targeted circuit using the plurality of ALUs on a basis of information relating to settings for a connection relationship of the plurality of ALUs and information relating to settings for each one of the plurality of ALUs, wherein
• the plurality of ALUs include a first type of ALU and a second type of ALU,
• the first type of ALU includes
• a first selection circuit that selects input data, and
• a first delay circuit that delays input data selected by the first selection circuit based on a clock signal and outputs a plurality of pieces of data with different delay amounts,
• the second type of ALU includes
• a second selection circuit that selects two pieces of data from a plurality of pieces of data including the plurality of pieces of data with different delay amounts from the first type of ALU and output data from another second type of ALU, according to settings set by the control unit, and outputs the two pieces of data as first data and second data,
• a second delay circuit that delays at least one of the first data and the second data by an amount according to the settings using a plurality of daisy-chained registers and then outputs the at least one of the first data and the second data, and
• an operation circuit that performs an operation according to the settings set by the control unit on data output from the second delay circuit,
• the second delay circuit
• includes a clock gate control circuit that controls supply and cutoff of a clock signal to the plurality of registers, and
• outputs the at least one of the first data and the second data without a delay in a state where supply of the clock signal to the plurality of registers is cut off.