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US 12,455,836 B2Granted
Victim cache that supports draining write-miss entries
AssigneeTexas Instruments Incorporated
InventorsNaveen Bhoria, Timothy David Anderson, Pete Hippleheuser
Life of this patent
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Abstract
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
Claims20
A device, comprising:
- a processor;
- a cache memory including:
- a cache line configured to store an entry;
- and
- a line type entry configured to store a value indicating whether the entry stored in the cache line is a write-miss entry or an entry evicted from another cache memory;
- an interface configured to couple the cache memory with the processor;
- and
- a controller configured to:
- determine whether the interface is in a state;
- and
- based on a determination that the interface is in the state, evict the entry from the cache line based on the value of the line type entry indicating that the entry stored in the cache line is a write-miss entry.
8 more elements
A method, comprising:
- storing data in a cache line of a cache memory;
- storing a value in a line type entry of the cache memory that indicates whether the data is associated with a write-miss entry or an entry evicted from another cache memory;
- detecting a state of an interface of the cache memory;
- and
- based on detecting the state, evicting the data from the cache line based on the value indicating that the data is associated with a write-miss entry.
2 more elements
Dependencies are inferred from the claim text.