Distributed error detection and correction with hamming code handoff

A method comprising:

• receiving, by a memory access arbiter, a memory access request associated with data and a memory address;
• generating, by the memory access arbiter, a first error correction code associated with the memory access request;
• receiving, by a plurality of components that includes a data path manager, the first error correction code;
• generating, by each component of the plurality of components, a first test error correction code associated with the memory access request;
• comparing, by each component of the plurality of components, the first test error correction code to the first error correction code to determine a number of bit errors associated with the first error correction code;
• in response to the number of bit errors indicating more than one bit error, transmitting, by each component of the plurality of components, an error code;
• and
• in response to the number of bit errors indicating a single bit error, correcting, by each component of the plurality of components, the single bit error.

A system comprising:

• a bus;
• a controller including a memory access arbiter configured to:
• receive a write access request that includes an address and data;
• generate an address error correction code;
• generate a data error correction code;
• and
• transmit the address error correction code, the data error correction code, and the data on the bus;
• and
• a plurality of components, including a data path manager, coupled to the bus, wherein each component of the plurality of components is configured to:
• generate a test address error correction code associated with the address of the write access request;
• compare the test address error correction code to the address error correction code to determine a first number of bit errors associated with the address error correction code;
• generate a test data error correction code associated with the data of the write access request;
• compare the test data error correction code to the data error correction code to determine a second number of bit errors associated with the data error correction code;
• in response to the first number of bit errors or the second number of bit errors indicating more than one bit error, transmit an error code on the bus;
• in response to the first number of bit errors indicating a first single bit error, correct the first single bit error;
• and
• in response to the second number of bit errors indicating a second single bit error, correct the second single bit error.