Low overhead error correction code

An apparatus comprising:

• a memory interface to couple a memory device to a compute core, wherein the memory interface comprises:
• decoder circuitry to:
• receive a protected version of a memory request from the compute core, wherein the protected version of a memory request comprises a compressed portion of the memory request, an error correction code, and a metadata bit;
• append a predefined pattern associated with a compression to the protected version of the memory request;
• perform a decoding of the protected version of the memory request with the appended predefined pattern to:
• determine, from the metadata bit, that compression was applied to the protected version of the memory request;
• and
• determine, from the error correction code and based on the compression applied to the protected version of the memory request, whether bit errors exist in the memory request.

A system comprising:

• a computing device;
• a memory device coupled to the computing device by an interface,
• wherein the computing device comprises:
• compression circuitry to:
• compare a subset of bits in a memory request to a pre-defined pattern to determine whether the subset of bits matches the pre-defined pattern;
• and
• compress the memory request based on a determination that the subset of bits in the memory request match the pre-defined pattern, wherein the memory request is compressed to generate a compressed version of the memory request, wherein compression of the memory request comprises removal of the subset of bits;
• and
• encoder circuitry to:
• generate an error correction code for the memory request;
• add the error correction code and at least one metadata bit to the compressed memory request to generate a protected version of the memory request, wherein the at least one metadata bit identifies whether compression is applied to the memory request, and a length of the protected version of the memory request is less than or equal to a length of the memory request;
• and
• transmitter circuitry to send the protected version of the memory request to the memory device;
• wherein the memory device comprises decoder circuitry to identify whether bit errors are present in the protected version of the memory request based on the error correction code.