Chip with power-glitch detection and power-glitch self-testing
AssigneeMediatek Inc.
InventorsPin-Wen Chen, Kuan-Chung Chen
Life of this patent
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Abstract
Power-glitch detection and power-glitch self-testing within a chip is shown. In a chip, a processor has a power terminal, a glitch detector, and a self-testing circuit. The power terminal is configured to receive power. The glitch detector is coupled to the power terminal of the processor for power-glitch detection. The self-testing circuit has a glitch generator and a glitch controller. The glitch controller controls the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector.
Claims20
A chip with power-glitch detection and power-glitch self-testing, comprising:
- a processor, having a power terminal configured to receive power;
- a glitch detector, coupled to the power terminal of the processor for power-glitch detection;
- a self-testing circuit, including a glitch generator and a glitch controller controlling the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector, wherein the glitch controller includes a phase-locked loop that generates a clock signal, shift registers operating according to the clock signal generated by the phase-locked loop, and a pulse generator driven by the shift registers to generate a pulse signal that is sent to the glitch generator to determine a pulse width of the self-testing glitch signal;
- and
- a frequency meter, configured to monitor malfunctions of the phase-locked loop or the shift registers.
A chip with power-glitch detection and power-glitch self-testing, comprising:
- a processor, having a power terminal configured to receive power;
- a glitch detector, coupled to the power terminal of the processor for power-glitch detection;
- a self-testing circuit, including a glitch generator and a glitch controller controlling the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector;
- a multiplexer, coupling the power terminal of the processor to the glitch detector while in a normal mode, and coupling the self-testing glitch signal to the glitch detector while in a power-glitch self-testing mode;
- a test pad;
- and
- a security switch, coupled between the test pad and a self-testing glitch input terminal of the multiplexer, wherein the self-testing glitch signal is coupled to the multiplexer through the self-testing glitch input terminal, wherein when an enable signal of the test pad is de-asserted to disable the test pad, the security switch blocks external glitch signals from entering through the test pad.
A chip with power-glitch detection and power-glitch self-testing, comprising:
- a processor, having a power terminal configured to receive power;
- a glitch detector, coupled to the power terminal of the processor for power-glitch detection;
- a self-testing circuit, including a glitch generator and a glitch controller controlling the glitch generator to generate a self-testing glitch signal within the chip to test the glitch detector;
- a multiplexer, coupling the power terminal of the processor to the glitch detector while in a normal mode, and coupling the self-testing glitch signal to the glitch detector while in a power-glitch self-testing mode;
- and
- a variable resistor, coupled between a power terminal of the chip and a self-testing glitch input terminal of the multiplexer for IR compensation;
- wherein the self-testing glitch signal is coupled to the multiplexer through the self-testing glitch input terminal.
Dependencies are inferred from the claim text.