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US 12,453,177 B2Granted
Integrated circuit including asymmetric ending cells and system-on-chip including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-kyu Ryu, Min-su Kim, Dae-seong Lee
Life of this patent
Estimating the term…
Abstract
An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.
Claims18
An integrated circuit comprising:
- a plurality of standard cells in a first area;
- a first plurality of dummy cells placed along portions of a boundary extending in a first direction around the plurality of standard cells, the first plurality of dummy cells abutting one another;
- a second plurality of dummy cells placed along a first portion of the boundary extending in a second direction around the plurality of standard cells, the second plurality of dummy cells abutting one another, each of the second plurality of dummy cells having a first width in the first direction;
- a third plurality of dummy cells placed along a second portion of the boundary extending in the second direction around the plurality of standard cells, the third plurality of dummy cells abutting one another, the third plurality of dummy cells being opposite to the second plurality of dummy cells with the plurality of standard cells therebetween, each of the third plurality of dummy cells having a second width in the first direction;
- one or more dummy cells placed along one or more remaining portions of the boundary not covered by the first plurality of dummy cells, the second plurality of dummy cells, and the third plurality of dummy cells to form a ring of dummy cells around the plurality of standard cells,
- a first macroblock adjacent to the second plurality of dummy cells;
- and
- a second macroblock adjacent to the third plurality of dummy cells,
- wherein the first plurality of dummy cells and the second plurality of dummy cells are placed at a distance inside the first area,
- wherein the first width is different from the second width,
- wherein each of the second plurality of dummy cells includes a tap configured to receive a power supply voltage or a ground voltage and provide the power supply voltage or the ground voltage to a first active region, and
- wherein each of the third plurality of dummy cells includes no tap such that the second width is less than the first width.
9 more elements
An integrated circuit comprising:
- a plurality of standard cells in a first area;
- a first plurality of dummy cells placed along portions of a boundary extending in a first direction around the plurality of standard cells, the first plurality of dummy cells abutting one another;
- a second plurality of dummy cells placed along a first portion of the boundary extending in a second direction around the plurality of standard cells, the second plurality of dummy cells abutting one another, each of the second plurality of dummy cells having a first width in the first direction;
- a third plurality of dummy cells placed along a second portion of the boundary extending in the second direction around the plurality of standard cells, the third plurality of dummy cells abutting one another, the second portion being opposite to the first portion, the third plurality of dummy cells being opposite to the second plurality of dummy cells with the plurality of standard cells therebetween, the third plurality of dummy cells being devoid of at least some devices or features present in the second plurality of dummy cells to be asymmetric in terms of size to the second plurality of dummy cells, each of the third plurality of dummy cells having a second width in the first direction;
- and
- one or more dummy cells placed along one or more remaining portions of the boundary not covered by the first plurality of dummy cells, the second plurality of dummy cells and the third plurality of dummy cells to form a ring of dummy cells around the plurality of standard cells,
- wherein the first plurality of dummy cells and the second plurality of dummy cells are placed at a distance inside the first area,
- wherein each of the second plurality of dummy cells includes a tap configured to receive a power supply voltage or a ground voltage and provide the power supply voltage or the ground voltage to an active region, and
- wherein each of the third plurality of dummy cells includes no tap such that the second width is less than the first width.
6 more elements
An integrated circuit comprising:
- a first macroblock and a second macroblock that are arranged in a first direction;
- and
- a plurality of cells arranged in a first area between the first macroblock and the second macroblock, the plurality of cells including,
- a plurality of standard cells,
- a first plurality of dummy cells placed along portions of a boundary extending in the first direction around the plurality of standard cells, the first plurality of dummy cells abutting one another,
- a second plurality of dummy cells placed along a first portion of the boundary extending in a second direction around the plurality of standard cells, the second plurality of dummy cells abutting one another, each of the second plurality of dummy cells having a first width in the first direction, the second plurality of dummy cells being adjacent to the first macroblock,
- a third plurality of dummy cells placed along a second portion of the boundary extending in the second direction around the plurality of standard cells, the third plurality of dummy cells abutting one another, the third plurality of dummy cells being opposite to the second plurality of dummy cells with the plurality of standard cells therebetween, each of the third plurality of dummy cells having a second width in the first direction, the third plurality of dummy cells being adjacent to the second macroblock;
- and
- one or more dummy cells placed along one or more remaining portions of the boundary not covered by the first plurality of dummy cells, the second plurality of dummy cells, and the third plurality of dummy cells, to form a ring of dummy cells around the plurality of standard cells,
- wherein the first plurality of dummy cells and the second plurality of dummy cells are placed at a distance inside the first area,
- wherein each of the second plurality of dummy cells includes a tap configured to receive a power supply voltage or a ground voltage and provide the power supply voltage or the ground voltage to an active region, and
- wherein each of the third plurality of dummy cells includes no tap such that the second width is less than the first width.
9 more elements
Dependencies are inferred from the claim text.