Transistors with stacked channels and the methods of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
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Abstract
A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
Claims20
A device comprising:
- a bulk semiconductor substrate;
- a semiconductor strip over the bulk semiconductor substrate;
- shallow trench isolation regions on opposite sides of the bulk semiconductor substrate;
- a plurality of semiconductor layers spaced apart from each other and overlapping the semiconductor strip, wherein upper ones of the plurality of semiconductor layers overlap respective lower ones of the semiconductor layers;
- a gate stack encircling the plurality of semiconductor layers, wherein the gate stack comprises:
- a gate dielectric comprising a plurality of portions, each encircling one of the plurality of semiconductor layers, wherein the plurality of portions comprise a same dielectric material, with the same dielectric material joined as a continuous layer that continuously extends into the plurality of portions;
- and
- a gate electrode encircling the gate dielectric;
- and
- source/drain regions connected to opposite ends of the plurality of semiconductor layers.
A device comprising:
- a bulk semiconductor substrate;
- a semiconductor strip over the bulk semiconductor substrate;
- shallow trench isolation regions on opposite sides of the bulk semiconductor substrate;
- a source region and a drain region comprising portions higher than the shallow trench isolation regions;
- a plurality of semiconductor layers connecting the source region to the drain region;
- a first dielectric layer encircling the plurality of semiconductor layers, wherein the first dielectric layer extends from the source region to the drain region;
- a second dielectric layer over and contacting the shallow trench isolation regions;
- and
- a gate electrode contacting the first dielectric layer, wherein the gate electrode separates the first dielectric layer from the second dielectric layer.
A device comprising:
- a first shallow trench isolation region;
- a second shallow trench isolation region spaced apart from the first shallow trench isolation region;
- a first semiconductor layer overlapping a space between the first shallow trench isolation region and the second shallow trench isolation region, wherein the first semiconductor layer is vertically aligned to the middle between the first shallow trench isolation region and the second shallow trench isolation region, and wherein the first semiconductor layer comprises:
- a first edge vertically aligned to a second edge of the first shallow trench isolation region;
- and
- a third edge vertically aligned to a fourth edge of the second shallow trench isolation region;
- and
- a gate stack comprising a gate dielectric and a gate electrode on the gate dielectric, wherein the gate stack fully encircles the first semiconductor layer.
Dependencies are inferred from the claim text.