Semiconductor transistor devices having double-sided interconnect structures

A semiconductor device comprising:

• a first semiconductor channel structure;
• a first gate structure on opposing sides of the first semiconductor channel structure along a first direction in a plan view;
• a first source/drain region adjacent the first semiconductor channel structure in a second direction in the plan view;
• a second semiconductor channel structure;
• a second gate structure on opposing sides of the second semiconductor channel structure along the first direction;
• a second source/drain region adjacent the second semiconductor channel structure in the second direction;
• a first interconnect structure on a first side of the first gate structure and the second gate structure;
• a source/drain contact electrically coupled to the first source/drain region, wherein the first source/drain region is between the source/drain contact and the first interconnect structure;
• and
• a first dielectric layer between the first gate structure and the second gate structure, a first surface of the first dielectric layer being level with a surface of the source/drain contact, a second surface of the first dielectric layer being level with a surface of the first gate structure.

A semiconductor device comprising:

• a first transistor structure comprising a first nanostructure, a first gate structure adjacent the first nanostructure, and a first source/drain region adjacent the first gate structure;
• a second transistor structure comprising a second nanostructure, a second gate structure adjacent the second nanostructure, and a second source/drain region adjacent the second gate structure;
• a first interconnect structure on a first side of the first transistor structure and the second transistor structure;
• and
• a second interconnect structure on a second side of the first transistor structure and the second transistor structure, the second interconnect structure comprising:
• a first dielectric layer on and between the first gate structure and the second gate structure;
• a first contact extending through the first dielectric layer to contact the second source/drain region, wherein a surface of the first dielectric layer is level with a surface of the first contact, wherein the surface of the first dielectric layer and the surface of the first contact face away from the first interconnect structure;
• and
• a first spacer between the first dielectric layer and the first contact.