High electron mobility transistor with reduced access resistance and method for manufacturing a high electron mobility transistor with reduced access resistance

A high electron mobility transistor comprising:

• a stack of layers comprising a passivation layer and a heterojunction comprising a first semiconductor layer, a second semiconductor layer and a two-dimensional electron gas at an interface thereof, one surface of the passivation layer being in contact with the first semiconductor layer;
• a source metal contact and/or a drain metal contact and a gate electrode;
• a n+ doped zone situated inside the heterojunction;
• the source metal contact or the drain metal contact, or both the source metal contact and the drain metal contact, being positioned at a level of a recess formed in the stack of layers, said source metal contact or said drain metal contact, or both the source metal contact and the drain metal contact, having a thickness defined by an upper face and a lower face substantially parallel to a plane of the layers, the upper face being planar, the lower face being in contact with the n+ doped zone and below the interface between the first semiconductor layer and the second semiconductor layer, said source metal contact or said drain metal contact, or both the source metal contact and the drain metal contact, further having a lateral face, the n+ doped zone extending from the lateral face of the source metal contact and/or from the lateral face of the drain metal contact to the gate electrode over a length comprised between 300 nm and 1000 nm.