Channel stop and well dopant migration control implant for reduced MOS threshold voltage mismatch

A metal-oxide-semiconductor (MOS) transistor, comprising:

• a semiconductor substrate having a well region having a first conductivity type;
• a gate formed over the well region;
• a source/drain region and a source/drain extension to the source/drain region formed in the substrate, both having a second conductivity type, the source/drain extension extending under the gate;
• a threshold voltage adjust region having the first conductivity type and a first profile peak depth within the semiconductor substrate;
• a channel stop region having the first conductivity type and a second profile peak depth within the semiconductor substrate that is deeper than the first profile peak depth;
• and
• a channel stop/well dopant migration control region overlapping the channel stop region and having a third profile peak depth that is at or less than the second profile peak depth.

An metal-oxide semiconductor (MOS) transistor, comprising:

• a semiconductor substrate having a well region having a first conductivity type;
• a gate formed over the well region;
• a source/drain region and a source/drain extension to the source/drain region formed in the substrate, both having a second conductivity type, the source/drain extension extending under the gate;
• a threshold voltage adjust region having the first conductivity type and a first profile peak depth within the semiconductor substrate;
• a channel stop region having the first conductivity type and a second profile peak depth within the semiconductor substrate that is deeper than the first profile peak depth;
• and
• a channel stop/well dopant migration control region comprising a nitrogen dopant and a carbon dopant that overlaps the channel stop region and has a third profile peak depth that is within ±250 nanometers of the second profile peak depth.