Trench gate high voltage transistor for embedded memory

A method for forming an integrated circuit (IC), the method comprising:

• providing a substrate including a logic region and a boundary region at a periphery of the logic region;
• forming a plurality of deep trenches from a top surface of the substrate, including a boundary trench in the boundary region and a logic device trench in the logic region;
• filling an isolation material in the plurality of deep trenches;
• removing the isolation material from the logic device trench;
• filling a first logic gate dielectric and a first logic gate electrode in the logic device trench;
• and
• forming first and second source/drain regions in the substrate on opposite sides of the logic device trench, wherein the first and second source/drain regions have a top surface coplanar with that of the first logic gate electrode.

A method for forming an integrated circuit (IC), the method comprising:

• providing a substrate including a memory region, a logic region, and a boundary region defined between the memory region and the logic region;
• forming a plurality of deep trenches from a top surface of the substrate, including a logic isolation trench in the logic region, a boundary trench in the boundary region, and a logic device trench in the logic region between the logic isolation trench and the boundary trench;
• filling an isolation material in the plurality of deep trenches;
• forming and patterning a multilayer film to form a plurality of memory cell structures on the memory region;
• forming a dummy capping layer overlying the memory cell structures;
• removing the isolation material from the logic device trench;
• filling a first logic gate dielectric and a first logic gate electrode in the logic device trench after removing the isolation material;
• and
• forming a hard mask layer on the first logic gate electrode within the logic device trench.