Printed circuit board and semiconductor package using the same

A printed circuit board comprising:

• a substrate structure having a first surface comprising a chip mounting region on which a semiconductor chip is mounted, and a second surface opposite to the first surface;
• and
• pad patterns disposed on the second surface of the substrate structure,
• wherein the second surface comprises:
• a first region comprising a region corresponding to the chip mounting region and in contact with respective edges of the second surface;
• and
• second regions adjacent to respective corners of the second surface and spaced apart from each other,
• wherein the pad patterns comprise first pad patterns surface-treated with a metal layer and second pad patterns surface-treated with an oxidation prevention layer,
• wherein the first pad patterns are disposed in the first region, and the second pad patterns are disposed in the second regions, respectively, and
• wherein a level of at least one lower surface of the first pad patterns surface-treated is lower than a level of at least one lower surface of the second pad patterns surface-treated.

A semiconductor package comprising:

• a semiconductor chip;
• a substrate structure having a first surface comprising a chip mounting region on which the semiconductor chip is mounted and a second surface, opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge, and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges;
• pad patterns disposed on the second surface of the substrate structure;
• and
• connection bumps respectively connected to the pad patterns,
• wherein the pad patterns comprise:
• first pad patterns disposed in a first region respectively adjacent to the first to fourth edges and comprising a region corresponding to the chip mounting region, in direct contact with the connection bumps, and the first pad patterns comprising a first metal material and having a metal layer comprising a second metal material disposed on an interface in contact with the connection bumps;
• and
• second pad patterns disposed in second regions respectively adjacent to the first to fourth corners, the second regions being regions other than the first region, the second pad patterns comprising the first metal material, and
• wherein a level of at least one lower surface of the first pad patterns is lower than a level of at least one lower surface of the second pad patterns.