Back to results
US 12,451,888 B1Granted
Ripple carry adder with ferroelectric or paraelectric wide-input minority or majority gates
AssigneeKepler Computing Inc.
InventorsAmrita Mathuriya, Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni
Life of this patent
Estimating the term…
Abstract
A low power adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. The adder may include minority gates and/or majority gates. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
Claims15
An apparatus comprising:
- a first 1-bit adder to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, wherein the third input is a carry-in input, wherein the third input is coupled to ground, and wherein the first 1-bit adder is to generate a first sum output and a first carry output;
- and
- a second 1-bit adder coupled to the first 1-bit adder, wherein the second 1-bit adder is to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input is a third operand, wherein the fifth input is a fourth operand, wherein the sixth input is a carry-in input, wherein the sixth input is coupled to the first sum output, wherein the second 1-bit adder is to generate a second sum output and a second carry output, wherein the first 1-bit adder includes a first set of input capacitors with non-linear polar material, wherein the second 1-bit adder includes a second set of input capacitors with the non-linear polar material, wherein the first set of input capacitors include at least three input capacitors, wherein first terminals of the at least three input capacitors are directly connected without magnets to the first input, the second input, and the third input respectively, and wherein second terminals of the at least three input capacitors are directly connected without magnets to a node.
A system comprising:
- a processor circuitry to execute one or more instructions;
- a communication interface communicatively coupled to the processor circuitry;
- and
- a memory coupled to the processor circuitry, wherein the processor circuitry comprises an adder circuitry which includes:
- a first 1-bit adder to receive a first input, a second input, and a third input, wherein the first input is a first operand, wherein the second input is a second operand, and wherein the third input is a carry-in input, wherein the third input is coupled to ground, and wherein the first 1-bit adder is to generate a first sum output and a first carry output;
- and
- a second 1-bit adder coupled to the first 1-bit adder, wherein the second 1-bit adder is to receive a fourth input, a fifth input, and a sixth input, wherein the fourth input is a third operand, wherein the fifth input is a fourth operand, and wherein the sixth input is a carry-in input, wherein the sixth input is coupled to the first sum output, wherein the second 1-bit adder is to generate a second sum output and a second carry output, wherein the first 1-bit adder includes a first set of input capacitors with non-linear polar material, wherein the second 1-bit adder includes a second set of input capacitors with the non-linear polar material, wherein the first set of input capacitors includes at least three input capacitors, wherein first terminals of the at least three input capacitors are directly connected without magnets to the first input, the second input, and the third input respectively, and wherein second terminals of the at least three input capacitors are directly connected without magnets to a node.
4 more elements
Dependencies are inferred from the claim text.