Apparatus comprising a comparator circuit

An apparatus comprising:

• a comparator circuit configured to compare a first input signal with a second input signal during a first comparison phase to acquire a comparison result;
• and to output an output signal, a waveform of the output signal being indicative of the comparison result;
• and to reset, during a subsequent regeneration phase, at least a portion of the comparator circuit for a subsequent second comparison phase;
• wherein the comparator circuit is configured to receive a clock signal and to change from the first comparison phase to the regeneration phase based on the clock signal;
• and
• a clock generation circuit configured to receive the output signal or a signal derived therefrom and to generate the clock signal based on the waveform of the output signal;
• to control the comparator circuit from the comparison phase to the regeneration phase depending on the waveform;
• wherein the clock generation circuit comprises a first circuit portion configured to output at a first circuit portion output a first intermediate signal indicating whether or not a comparison result is present;
• wherein the apparatus comprises a second circuit portion configured to derive the clock signal from the first intermediate signal;
• and at least one of:
• wherein the comparator circuit is configured to provide the output signal as a first partial signal and a second partial signal;
• and is configured to indicate the comparison result starting from a reference state acquired by a preceding regeneration phase by means of a level change in exclusively one of the first partial signal and the second partial signal;
• wherein the first circuit portion is formed as a first XOR gate and the first partial signal and the second partial signal are coupled to inputs of the first XOR gate;
• wherein the second circuit portion comprises:
• a signal source configured to provide a control signal comprising a first control signal level for the duration of a measurement interval for performing at least the first comparison phase;
• a second XOR gate connected on the input side to the signal source and to the first circuit portion output;
• and configured to provide the clock signal based on a combination of the control signal and the first intermediate signal;
• wherein the second circuit portion comprises:
• a third XOR gate;
• wherein an output of the third XOR gate is coupled to a first input of the second XOR gate;
• and a second input of the second XOR gate is coupled to the first circuit portion output to receive the first intermediate signal;
• wherein the third XOR gate is configured to provide a second intermediate signal at a signal output;
• wherein the second XOR gate is configured to provide, based on a combination of the first intermediate signal and the second intermediate signal, the clock signal at an output of the second XOR gate coupled to the comparator circuit on the one hand and to the first input of the third XOR gate on the other hand;
• wherein the second circuit portion comprises:
• a continuous signal source configured to provide a constant control signal;
• a controller configured to supply the continuous signal source and the comparator circuit with a power for operating the continuous signal source and the comparator circuit for the duration of a measurement interval for performing at least the first comparison phase;
• the second XOR gate coupled on the input side to the continuous signal source and to the first circuit portion output;
• and configured to provide the clock signal based on a combination of the constant control signal and the first intermediate signal;
• and
• wherein the second circuit portion comprises:
• an inverter circuit coupled to the first circuit portion and configured to invert the first intermediate signal to acquire an inverted intermediate signal;
• and to acquire the clock signal based on the inverted intermediate signal;
• wherein the apparatus further comprises a controller configured to terminate operation of the inverter circuit after a number of at least one measurement interval of the apparatus;
• and when the inverter circuit is switched on again, to acquire a state of the comparator circuit comparable to a reference state acquired by means of the regeneration phase for a subsequent measurement interval;
• and to generate the clock signal again when the inverter circuit is switched on again.