US 12,451,875 B2 · High-voltage Schmitt trigger

Abstract

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.

Claims18

Dependent claims

A structure comprising:

a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail;
a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET,
wherein gates of the first PFET and the first NFET are connected to an input node to receive an input voltage, and
wherein gates of the second PFET and the second NFET are connected to receive different reference voltages;
an output node connected to a first intermediate node between the second PFET and the second NFET;
a third PFET connected between the ground rail and a second intermediate node between the first PFET and the second PFET;
a fourth PFET connected between a gate of the third PFET and the output node;
a third NFET connected between the positive voltage rail and a third intermediate node between the first NFET and the second NFET;
and
a fourth NFET connected between a gate of the third NFET and the output node.

7 more elements

A structure comprising:

a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail;
and
a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET,
wherein gates of the first PFET and the first NFET are connected to an input node to receive an input voltage, and
wherein gates of the second PFET and the second NFET are connected to receive different variable reference voltages;
an output node connected to a first intermediate node between the second PFET and the second NFET;
a third PFET connected between the ground rail and a second intermediate node between the first PFET and the second PFET;
a fourth PFET connected between a gate of the third PFET and the output node;
a third NFET connected between the positive voltage rail and a third intermediate node between the first NFET and the second NFET;
and
a fourth NFET connected between a gate of the third NFET and the output node.

8 more elements

A structure comprising:

a first p-channel field effect transistor (PFET) and a second PFET connected in series to a positive voltage rail;
and
a first n-channel field effect transistor (NFET) and a second NFET connected in series between a ground rail and the second PFET,
wherein the first PFET and the first NFET are buried oxide field effect transistors (BOXFETs),
wherein the second PFET and the second NFET are laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs),
wherein gates of the first PFET and the first NFET are connected to an input node, and
wherein gates of the second PFET and the second NFET are connected to receive different variable reference voltages.

4 more elements

Dependencies are inferred from the claim text.

High-voltage Schmitt trigger

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High-voltage Schmitt trigger

Life of this patent

Abstract

Claims18