Wafer level package

A wafer level package, comprising:

• a substrate (SU) having a functional layer and electric device structures (DS) realized in the functional layer, on the functional layer or under the functional layer;
• a first package layer (PL1) applied on the substrate, the first package layer defining cavities (CV) between the substrate and the first package layer, at least part of the device structures being arranged in the cavities;
• a second package layer (PL2) applied over a surface of the first package layer;
• pads (PD) arranged on the substrate and connected to the device structures, a partial area of each pad forming a respective contact area that is not covered by the first package layer or the second package layer;
• an interconnect structure (IS) deposited on each respective contact area and extending up to an interconnect height (hi) over the substrate, the interconnect height being higher than a package height (hp) of the first package layer and the second package layer over the substrate;
• and
• solder caps (SC) disposed at a respective distal end of each respective interconnect structure.