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US 12,451,411 B2Granted
Structure with air gaps extending from dielectric liner around through semicondcutor via
AssigneeGlobalFoundries U.S. Inc.
InventorsDewei Xu, Zhuojie Wu, Daniel Smith
Life of this patent
Estimating the term…
Abstract
A structure includes a through semiconductor via (TSV) in a semiconductor substrate, and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate. A plurality of discontinuous air gaps is in the semiconductor substrate extending away from the dielectric liner, e.g., radially. The discontinuous air gaps reduce the parasitic coupling capacitance and relieve stress in the semiconductor substrate.
Claims20
A structure, comprising:
- a through semiconductor via (TSV) in a semiconductor substrate;
- a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate;
- and
- a plurality of discontinuous air gaps in the semiconductor substrate extending away from the dielectric liner and including at least one sidewall immediately contacting the semiconductor substrate.
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A structure, comprising:
- a through semiconductor via (TSV) in a semiconductor substrate;
- a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate;
- and
- a plurality of elongated air gaps in the semiconductor substrate adjacent to the dielectric liner, each air gap having a first sidewall contacting the dielectric liner and a second sidewall distanced from the dielectric liner and immediately contacting the semiconductor substrate.
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A method comprising:
- forming a through semiconductor via (TSV) in a frontside of a semiconductor substrate and a dielectric liner surrounding the TSV and between the TSV and the semiconductor substrate;
- forming a plurality of elongated air gaps in the semiconductor substrate adjacent to the dielectric liner, each air gap having a first sidewall contacting the dielectric liner and a second sidewall distanced from the dielectric liner and immediately contacting the semiconductor substrate;
- and
- planarizing a backside of the semiconductor substrate to complete the TSV.
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Dependencies are inferred from the claim text.