Semiconductor metal layer structure over cell region

An integrated circuit, comprising:

• a first cell,
• a second cell abutting the first cell;
• a metal-to-diffusion (MD) layer extending over the first cell and the second cell;
• gates extending over the first cell and the second cell;
• a first metallization layer including MD tracks disposed over the MD layer and the gates;
• and
• a second metallization layer including M1 tracks disposed over the first metallization layer, the M1 tracks including first M1 tracks and second M1 tracks, wherein the first M1 tracks are longer than the second M1 tracks, wherein the first M1 tracks of the first cell align with the second M1 tracks of the second cell, and wherein the second M1 tracks of the first cell align with the first M1 tracks of the second cell.

A method of forming a cell layout structure, the method comprising:

• forming a metal diffusion (MD) layer and gates over an active region of one or more cells;
• forming a first metallization layer including MD tracks over the one or more cells;
• and
• forming a second metallization layer including M1 tracks over the first metallization layer, wherein first M1 tracks are disposed a first predetermined distance from an edge of a cell, wherein second M1 tracks are disposed a second predetermined distance from the edge of the cell, wherein the first M1 tracks are longer than the second M1 tracks, and wherein the first predetermined distance is smaller than the second predetermined distance.