Caching host memory address translation data in a memory sub-system

A method comprising:

• buffering, within a set of request staging queues of an address translation circuit, address translation requests received from host interface circuits, wherein each address translation request comprises a virtual address;
• storing, within a set of pending response queues, respective address translation requests that are waiting for an address translation from a host system while maintaining an order as received within the set of request staging queues;
• reordering, within a set of reordering buffers, address translations according to the order of the address translation requests maintained within the set of pending response queues, wherein each address translation comprises a physical address mapped to a respective virtual address;
• sending, from the set of reordering buffers, each of the address translations to a corresponding host interface circuit of the host interface circuits that sent a corresponding address translation request;
• and
• storing, in a cache coupled with the set of request staging queues and the set of reordering buffers, a plurality of the address translations, associated with the address translations requests, for future access by the host interface circuits.

A system comprising:

• host interface circuitry comprising a plurality of host interface circuits to interact with a host system;
• and
• an address translation circuit of the host interface circuitry to handle address translation requests from the plurality of host interface circuits, the address translation circuit comprising:
• a set of request staging queues to buffer the address translation requests, each address translation request comprising a virtual address and received from one of the plurality of host interface circuits;
• a set of reordering buffers to reorder address translations, which are to be supplied to the plurality of host interface circuits, according to an order of corresponding address translation requests received within the set of request staging queues;
• a cache coupled to the set of reordering buffers;
• and
• translation logic coupled to the set of request staging queues, the set of reordering buffers, and the cache, the translation logic to:
• store, in the cache, a plurality of the address translations associated with the address translation requests;
• and
• reinsert, into the set of reordering buffers, a first address translation from the cache for a subsequent request for the first address translation by a host interface circuit of the plurality of host interface circuits.