Firmware repair for three-dimensional NAND memory
AssigneeYangtze Memory Technologies Co., Ltd.
InventorYanLan Liu
Life of this patent
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Abstract
The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.
Claims20
A content addressable memory (CAM), comprising:
- a CAM register configured to store a mapping table, wherein the mapping table comprises first addresses and second addresses, each one of the first addresses corresponding to one of the second addresses;
- N comparators coupling to the CAM register, wherein each of the N comparators is configured to compare the first addresses with one of N input signals, where Nis an integer greater than 1, and the N input signals come from N microcontroller units;
- and
- N multiplexers coupling to the N comparators respectively and to the CAM register, and configured to generate N output signals, wherein at least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.
A content addressable memory (CAM), comprising:
- a CAM register configured to store a mapping table, wherein the mapping table comprises first addresses and second addresses, each one of the first addresses corresponding to one of the second addresses;
- a first comparator and a second comparator both coupled to the CAM register, the first comparator being configured to receive a first input signal of a first microcontroller unit and compare the first input signal with the first addresses, the second comparator being configured to receive a second input signal of a second microcontroller unit and compare the second input signal with the first addresses;
- and
- a first multiplexer and a second multiplexer both coupled to the CAM register and configured to receive the second addresses, the first multiplexer coupling to the first comparator, the second multiplexer coupling to the second comparator.
A memory device, comprising:
- M memory planes, wherein M is an integer greater than 1;
- and
- a control circuit coupling to the M memory planes by at least one of a word line driver or a bit line driver, wherein the control circuit comprises:
- M microcontroller units, each configured to provide a read control signal for a respective memory plane of the M memory planes;
- and
- a content addressable memory (CAM) comprising a CAM register shared by the M microcontroller units.
Dependencies are inferred from the claim text.