Enabling high-performance scalable matrix extension (SME) instruction issue in processor devices

A processor device, comprising:

• means for performing, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on each micro-operation (micro-op) of a plurality of micro-ops, stored by a reservation station circuit of the processor device, for which corresponding vector (Z) registers of a plurality of Z registers of the processor device and corresponding predicate (P) registers of a plurality of P registers of the processor device are ready;
• means for selecting, during the first phase based on the reduced-precision ZA tracking operation, a first micro-op and a second micro-op for which the reduced-precision ZA tracking operation indicates no Read-After-Write (RAW) hazard exists with respect to a plurality of ZA registers of the processor device;
• means for performing, during a subsequent second phase, a full-precision ZA tracking operation on each of the first micro-op and the second micro-op;
• means for selecting, during the subsequent second phase based on the full-precision ZA tracking operation, one of the first micro-op and the second micro-op as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the plurality of ZA registers;
• and
• means for issuing, during the subsequent second phase, the micro-op for issue to an execution circuit of an instruction processing circuit of the processor device for execution.

A method for enabling Scalable Matrix Extension (SME) instruction issue, comprising:

• during a first phase:
• performing, by a reservation station circuit of a processor device, a reduced-precision vector accumulator (ZA) tracking operation on each micro-operation (micro-op) of a plurality of micro-ops, stored by the reservation station circuit, for which corresponding vector (Z) registers of a plurality of Z registers of the processor device and corresponding predicate (P) registers of a plurality of P registers of the processor device are ready;
• and
• selecting, by the reservation station circuit based on the reduced-precision ZA tracking operation, a first micro-op and a second micro-op for which the reduced-precision ZA tracking operation indicates no Read-After-Write (RAW) hazard exists with respect to a plurality of ZA registers of the processor device;
• and
• during a subsequent second phase:
• performing, by the reservation station circuit, a full-precision ZA tracking operation on each of the first micro-op and the second micro-op;
• selecting, by the reservation station circuit based on the full-precision ZA tracking operation, one of the first micro-op and the second micro-op as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the plurality of ZA registers;
• and
• issuing, by the reservation station circuit, the micro-op for issue to an execution circuit of an instruction processing circuit of the processor device for execution.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed by a processor device, cause a dependency identifier circuit of the processor device to:

• during a first phase:
• perform a reduced-precision vector accumulator (ZA) tracking operation on each micro-operation (micro-op) of a plurality of micro-ops, stored in a reservation station circuit of the processor device, for which corresponding vector (Z) registers of a plurality of Z registers of the processor device and corresponding predicate (P) registers of a plurality of P registers of the processor device are ready;
• and
• select, based on the reduced-precision ZA tracking operation, a first micro-op and a second micro-op for which the reduced-precision ZA tracking operation indicates no Read-After-Write (RAW) hazard exists with respect to a plurality of ZA registers of the processor device;
• and
• during a subsequent second phase:
• perform a full-precision ZA tracking operation on each of the first micro-op and the second micro-op;
• select, based on the full-precision ZA tracking operation, one of the first micro-op and the second micro-op as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the plurality of ZA registers;
• and
• issue the micro-op for issue to an execution circuit of an instruction processing circuit of the processor device for execution.