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US 12,449,478 B2Granted
Low overhead loop back test for high speed transmitter
AssigneeSTMicroelectronics International N.V.
InventorsRupesh Singh, Ankur Bal
Life of this patent
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Abstract
An integrated circuit includes a serializer configured to receive first test data in n-bit words and to generate a single bit data stream by serializing the test data in accordance with a first clock signal. The integrated circuit includes testing circuitry configured to test the serializer without utilizing a deserializer.
Claims20
A method, comprising:
- dividing a first clock signal having a first frequency to obtain a second clock signal having a second frequency lower than the first frequency;
- providing first test data in a series of words to a serializer in accordance with the second clock signal;
- generating, at the serializer, a single bit data stream by serializing the test data in accordance with the first clock signal;
- generating a plurality of phase signals offset from each other in phase and each having the second frequency;
- and
- generating second test data by sampling the single bit data stream in accordance with each of the plurality of phase signals.
3 more elements
An integrated circuit, comprising:
- a phase signal generator configured to receive a first clock signal having a first frequency, to generate a second clock signal having a second frequency lower than the first frequency by diving the first clock signal, and to generate a plurality of phase signals each having the second frequency;
- a test data generator configured to output first test data in accordance with the second clock signal;
- a serializer configured to generate a single bit data stream by serializing the first test data in accordance with the first clock signal, the serializer including:
- an input coupled to the test data generator and configured to receive the test data;
- and
- an output configured to output the single bit data stream;
- a phase selector including:
- a plurality of inputs each configured to receive a respective phase signal of the plurality of phase signals;
- and
- an output configured to output a selected phase signal of the plurality of phase signals;
- a flip-flop including:
- a clock input terminal coupled to the output of the phase selector and configured to receive the selected phase signal;
- a data input terminal coupled to an output of the serializer;
- and
- a data output terminal.
12 more elements
An integrated circuit, comprising:
- a phase signal generator configured to generate, from a first clock signal having a first frequency, a second clock signal and n phase signals each having a second frequency that is 1/nth a frequency of the first clock signal, the n phase signals being out of phase with each other, where n is an integer number;
- a test data generator configured to output first test data in n-bit words in accordance with the second clock signal;
- a serializer configured to receive the first test data from the test data generator and to serialize the test data in accordance with the first clock signal to generate a single bit data stream;
- a phase selector configured to receive the n phase signals and to sequentially output the n phase signals one at a time based on a phase selection signal;
- and
- a flip-flop configured to receive, on a clock terminal, the n phase signals from the phase selector, and to receive the single bit data stream on a data input terminal.
3 more elements
Dependencies are inferred from the claim text.