Method for predicting failure of semiconductor device, and semiconductor device

A semiconductor device including a semiconductor element having a trench gate structure configured by connecting main cells in parallel, the semiconductor device comprising:

• a semiconductor substrate including a main cell region and an outer peripheral region surrounding the main cell region, the main cell region being a region where the main cells are disposed and including first cells and second cells as the main cells, the second cells having a structure in which gate insulating films are more easily broken by energization than gate insulating films in the first cells in order to predict failure of the first cells, a number of the second cells being smaller than a number of the first cells;
• gate pads disposed on one surface of the semiconductor substrate for applying a gate drive voltage to gate electrodes of the main cells, the gate pads including a first pad connected to the gate electrodes of the first cells and second pads disposed separately from the first pad and connected to the gate electrodes of the second cells;
• and
• switches including a first switch connected to the first pad and second switches connected to the second pads, individually disposed for the gate pads, and configured to allow or block application of the gate drive voltage to the gate pads, wherein
• at a time of driving the semiconductor element, all of the switches are turned on when no failure has occurred in the second cells, and only one or more of the second switches corresponding to one or more of the second cells that have failed are turned off and remaining switches in the switches are turned on when failure has occurred in the second cells, and
• at a time of non-driving the semiconductor element, the first switch is turned off and one or more of the second switches are turned on.

A semiconductor device including a semiconductor element having a trench gate structure configured by connecting main cells in parallel, the semiconductor device comprising:

• a semiconductor substrate including a main cell region and an outer peripheral region surrounding the main cell region, the main cell region being a region where the main cells are disposed and including first cells and second cells as the main cells, the second cells having a structure in which gate insulating films are more easily broken by energization than gate insulating films in the first cells in order to predict a failure of the first cells, a number of the second cells being smaller than a number of the first cells;
• gate pads disposed on one surface of the semiconductor substrate for applying a gate drive voltage to gate electrodes of the main cells, the gate pads including a first pad connected to the gate electrodes of the first cells and second pads disposed separately from the first pad and connected to the gate electrodes of the second cells;
• and
• fuses individually connecting the second pads and the first pad, wherein
• the fuses are configured such that, in association with failure of one or more of the second cells, one or more of the fuses that are connected to one or more of the second pads corresponding to the one or more of the second cells melt.