Charging protection circuit, charging circuit, and electronic device

A charging protection circuit, comprising:

• a first four-terminal N-type metal oxide semiconductor NMOS switching transistor, comprising a first drain, a second drain, a gate, and a Sub port, wherein the first drain is connected to a first power supply interface, the second drain is connected to a load, and the gate is connected to a drive circuit;
• and
• a Sub port management circuit, comprising a pull-up circuit connected to the Sub port, wherein the pull-up circuit is configured to:
• when the first four-terminal NMOS switching transistor is turned on, pull up potential of the Sub port to a potential of the first drain or the second drain, wherein the pull-up circuit comprises a first three-terminal NMOS switching transistor;
• and
• a drain of the first three-terminal NMOS switching transistor is connected to the first drain of the first four-terminal NMOS switching transistor, a source of the first three-terminal NMOS switching transistor is connected to the Sub port, a gate of the first three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables both the first three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on,
• wherein the pull-up circuit further comprises a second three-terminal NMOS switching transistor;
• and a drain of the second three-terminal NMOS switching transistor is connected to the second drain of the first four-terminal NMOS switching transistor, a source of the second three-terminal NMOS switching transistor is connected to the Sub port, a gate of the second three-terminal NMOS switching transistor is connected to the drive circuit, and the drive voltage provided by the drive circuit enables both the second three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on,
• wherein a threshold voltage of the second three-terminal NMOS switching transistor and the threshold voltage of the first four-terminal NMOS switching transistor have a same value, and the drive circuit is configured to provide drive voltages with a same phase for the gate of the first four-terminal NMOS switching transistor and the gate of the second three-terminal NMOS switching transistor.

A charging protection circuit, comprising:

• a first four-terminal N-type metal oxide semiconductor NMOS switching transistor, comprising a first drain, a second drain, a gate, and a Sub port, wherein the first drain is connected to a first power supply interface, the second drain is connected to a load, and the gate is connected to a drive circuit;
• and
• a Sub port management circuit, comprising a pull-up circuit connected to the Sub port, wherein the pull-up circuit is configured to:
• when the first four-terminal NMOS switching transistor is turned on, pull up potential of the Sub port to a potential of the first drain or the second drain, wherein the pull-up circuit comprises a first three-terminal NMOS switching transistor;
• and
• a drain of the first three-terminal NMOS switching transistor is connected to the first drain of the first four-terminal NMOS switching transistor, a source of the first three-terminal NMOS switching transistor is connected to the Sub port, a gate of the first three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables both the first three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on,
• wherein the Sub port management circuit further comprises a pull-down circuit, and the pull-down circuit is connected to the Sub port, and is configured to:
• when the first four-terminal NMOS switching transistor is turned off, pull down the potential of the Sub port to zero potential,
• wherein the pull-down circuit comprises a further three-terminal NMOS switching transistor;
• and
• a source of the further three-terminal NMOS switching transistor is grounded, a drain of the further three-terminal NMOS switching transistor is connected to the Sub port, a gate of the further three-terminal NMOS switching transistor is connected to the drive circuit, and a drive voltage provided by the drive circuit enables one of the further three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor to be turned on while the other one of the further three-terminal NMOS switching transistor and the first four-terminal NMOS switching transistor is turned off,
• wherein the drive circuit comprises a pulse width modulation PWM module and a charge pump;
• a first input terminal of the charge pump is connected to an output terminal of the PWM module, and is configured to receive a control logic voltage Vpwm input by the charge pump;
• a second input terminal of the charge pump is connected to the first power supply interface, and is configured to receive a bus voltage Vbus input from the first power supply interface, and an output terminal of the charge pump is connected to the gate of the first four-terminal NMOS switching transistor;
• and
• the charge pump processes, under control of Vpwm, Vbus to obtain an output voltage Vout, and applies Vout to the gate of the first four-terminal NMOS switching transistor.