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US 12,446,265 B2Granted
Semiconductor devices and methods for manufacturing the same, and NAND memory devices
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsLan Yao, Ziqun Hua, Yanwei Shi
Life of this patent
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Abstract
A semiconductor device and a method for manufacturing the same, and a NAND memory device are disclosed. The method comprises: forming a substrate that comprises a first active region and an isolation region; forming a first groove between the isolation region and the first channel region, the first groove being partially located in the isolation region, and not penetrating through the isolation region; forming a first gate insulating layer covering the first groove and the first channel region; forming a first gate on the first gate insulating layer, the first gate covering the first channel region and filling the first groove.
Claims20
A semiconductor device, comprising:
- a substrate comprising a first active region, a second active region, and an isolation region surrounding the first active region, the first active region comprising a first channel region sandwiched between a first source region and a first drain region in a lateral direction, the first active region and the second active region are separated by the isolation region, and the second active region comprising a second channel region sandwiched between a second source region and a second drain region in the lateral direction;
- a first groove located between the isolation region and the first channel region, the first groove being partially located in the isolation region without penetrating the isolation region;
- a second groove located between the isolation region and the second channel region, the second groove being partially located in the isolation region without penetrating the isolation region;
- a first gate insulating layer covering the first groove and the first channel region;
- a second gate insulating layer covering the second groove and the second channel region, a thickness of the second gate insulating layer being different from a thickness of the first gate insulating layer;
- and
- a first gate located on the first gate insulating layer, and covering the first channel region and filling the first groove.
4 more elements
A NAND memory device, comprising:
- a memory array comprising a plurality of memory cell strings;
- and
- a periphery device electrically connected with the memory array, comprising:
- a substrate comprising a first active region, a second active region, and an isolation region separating the first active region and the second active region, the first active region comprising a first channel region sandwiched between a first source region and a first drain region in a lateral direction, and the second active region comprising a second channel region sandwiched between a second source region and a second drain region in the lateral direction,
- a first groove located between the isolation region and the first channel region, the first groove being partially located in the isolation region without penetrating the isolation region,
- a second groove located between the isolation region and the second channel region, the second groove being partially located in the isolation region without penetrating the isolation region,
- a first gate insulating layer covering the first groove and the first channel region,
- a second gate insulating layer covering the second groove and the second channel region, a thickness of the second gate insulating layer being different from a thickness of the first gate insulating layer, and
- a first gate located on the first gate insulating layer, the first gate covering the first channel region and filling the first groove.
6 more elements
A semiconductor device, comprising:
- a substrate comprising a first active region, a second active region, and an isolation region between the first active region and the second active region, the first active region comprising a first channel region, and the second active region comprising a second channel region;
- a first groove located between the isolation region and the first channel region;
- a second groove located between the isolation region and the second channel region;
- a first gate insulating layer covering the first groove and the first channel region;
- a second gate insulating layer covering the second groove and the second channel region, a thickness of the second gate insulating layer being different from a thickness of the first gate insulating layer;
- and
- a first gate located on the first gate insulating layer, comprising a first lateral portion covering the first channel region and a first extended portion in the first groove;
- and
- a second gate located on the second gate insulating layer, comprising a second lateral portion covering the second channel region and a second extended portion in the second groove.
6 more elements
Dependencies are inferred from the claim text.