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US 12,446,236 B2Granted
Resistive random-access memory using stacked technology
AssigneeW&Wram Devices, Inc.
InventorsShih-Yuan Wang, Shih-Ping Wang
Life of this patent
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Abstract
Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described in combination with stacked technology with CMOS ASIC wafters. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. Stacking technology can be used to address incompatibility of ReRAM processing and CMOS ASICs processing.
Claims20
A stacked device comprising:
- an active transistor circuit (120);
- a resistive random-access memory (110) stacked on and integrated with the active transistor circuit and comprising:
- top (510) and bottom (530) electrodes and a switching layer (540) between the top electrode and the bottom electrode;
- a switching region (520) that is within said switching layer and is laterally flanked by portions of said switching layer that are not a switching region;
- wherein said switching region is formed by ion implantation into the switching layer through at least one of the top electrode and bottom electrode;
- wherein said switching region is configured to switch between high and low electrical conductivity in response to the application of a switching voltage without a need of applying a breakdown voltage to form said switching region;
- and
- a connecting electrode (734) electrically coupling at least one of the top electrode and the bottom electrode to the active transistor circuit.
5 more elements
A stacked device comprising:
- an active transistor circuit (120);
- a resistive random access memory (110) stacked on and integrated with the active transistor circuit and comprising:
- top (510) and bottom (530) electrodes and a layer of non-switching material (520) into which switching species have been implanted to form a switching channel (520);
- wherein said material has an area in planes along said top and bottom electrodes and said switching channel area in said planes is less than that of said material;
- wherein said switching channel is configured to switch between high and low electrical conductivity in response to the application of a switching voltage below a breakdown voltage without a need of applying a breakdown voltage to form said switching channel;
- and
- a connecting electrode (734) electrically coupling at least one of the top electrode and the bottom electrode to the active transistor circuit.
4 more elements
A method of forming a stacked device, comprising:
- providing a stack of a semiconductor material having a first layer (722) for a resistive random-access memory and a second layer (732) for an active transistor circuit;
- forming a connecting electrode (734) that extends from a region of the second layer toward a region of the first layer and a bottom electrode that is at a region of the first layer and merges with a top of said connecting electrode and top electrode at an upper region of the first layer;
- ion implanting through the top electrode and into the material of the first layer to form a switching region (720) extending from the top to the bottom electrodes and flanked by said material of the first layer at least on two sides;
- wherein said switching region is configured to switch between high and low electrical conductivity in response to the application of a switching voltage without a need of applying a breakdown voltage to form said switching region;
- and
- wherein the step of forming the switching region comprises forming the switching region with a substantially constant width from said top electrode to said bottom electrode.
3 more elements
A method of forming a stacked device, comprising:
- providing a stack of a semiconductor material having a first layer (722) for a resistive random-access memory and a second layer (732) for an active transistor circuit;
- wherein said first layer is a non-switching material;
- forming a connecting electrode (734) that extends from a region of the second layer toward a region of the first layer and a bottom electrode (730) that is at a region of the first layer and merges with a top of said connecting electrode and a top electrode (710) at an upper region of the first layer;
- ion implanting switching species through the top electrode and into the material of the first layer to form a switching region (720) extending from the top to the bottom electrodes and flanked by said non-switching material of the first layer at least on two sides;
- wherein said switching region is configured to switch between high and low electrical conductivity in response to the application of a switching voltage without a need of applying a breakdown voltage to form said switching region.
2 more elements
Dependencies are inferred from the claim text.