# US 12,446,219 B2 · Small-area common-voltage multi-write non-volatile memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,446,219 B2 - Document ID: US12446219B2 - Status: Granted - Kind: B2 - Application number: 18/480,722 - Filed: 2023-10-04 - Published: 2025-01-09 - Granted: 2025-10-14 - Earliest claimed: 2023-07-06 - Assignees: Yield Microelectronics Corp. - Applicants: Yield Microelectronics Corp. - Inventors: Yu-Ting Huang; Chi-Pei Wu - Web page: https://patentgrep.com/patent/US12446219B2 ## CPC - H10B 41/70: the floating gate being an electrode shared by two or more components - G11C 16/0441: {comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/20: Initialising; Data preset; Chip identification - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/35: with a cell select transistor, e.g. NAND - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A small-area common-voltage multi-write non-volatile memory array includes word lines, select lines, common-voltage lines, and sub-memory arrays. The word lines include a first word line and a second word line. The select lines include a first select line. The common-voltage lines are directly coupled together. The common-voltage lines include a first common-voltage line and a second common-voltage line. Each sub-memory array includes a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line. ## Claims ### Claim 1 A small-area common-voltage multi-write non-volatile memory array comprising: a plurality of word lines, arranged in parallel, comprising a first word line and a second word line; a plurality of select lines arranged in parallel, wherein the plurality of select lines perpendicular to the plurality of word lines comprise a first select line; a plurality of common-voltage lines arranged in parallel, wherein the plurality of common-voltage lines perpendicular to the plurality of select lines are directly coupled together, the plurality of common-voltage lines comprise a first common-voltage line and a second common-voltage line, and the first word line and the second word line are respectively close to the first common-voltage line and the second common-voltage line, wherein the first word line and the second word line are arranged between the first common-voltage line and the second common-voltage line; and a plurality of sub-memory arrays each coupled to two of the plurality of word lines, one of the plurality of select lines, and two of the plurality of common-voltage lines, wherein each of the plurality of sub-memory arrays comprises: a first non-volatile memory cell coupled to the first word line, the first select line, and the first common-voltage line; and a second non-volatile memory cell coupled to the second word line, the first select line, and the second common-voltage line. ### Claim 2 (depends on 1) The small-area common-voltage multi-write non-volatile memory array according to claim 1, wherein the first non-volatile memory cell and the second non-volatile memory cell are arranged symmetric to each other. ### Claim 3 (depends on 2) The small-area common-voltage multi-write non-volatile memory array according to claim 2, wherein the first non-volatile memory cell and the second non-volatile memory cell are formed in a P-type semiconductor region, and the first non-volatile memory cell comprises: a first gate dielectric block, formed on the P-type semiconductor region and arranged between the first word line and the P-type semiconductor region, comprising a high dielectric constant material; a first common-voltage gate formed on the first gate dielectric block and coupled to the first common-voltage line, wherein the first common-voltage gate is closer to the first common-voltage line than the first word line and the first common-voltage gate comprises high dielectric constant metal; and a first N-type doped region, a second N-type doped region, and a third N-type doped region formed in the P-type semiconductor region, wherein the first N-type doped region and the second N-type doped region are respectively formed on two opposite side of the P-type semiconductor region, which is directly arranged under the first word line, the second N-type doped region and the third N-type doped region are respectively formed on two opposite side of the P-type semiconductor region, which is directly arranged under the first common-voltage gate, and the first N-type doped region is coupled to the first select line. ### Claim 4 (depends on 3) The small-area common-voltage multi-write non-volatile memory array according to claim 3, wherein the second non-volatile memory cell comprises: a second gate dielectric block, formed on the P-type semiconductor region and arranged between the second word line and the P-type semiconductor region, comprising a high dielectric constant material; a second common-voltage gate formed on the second gate dielectric block and coupled to the second common-voltage line, wherein the second common-voltage gate is closer to the second common-voltage line than the second word line and the second common-voltage gate comprises high dielectric constant metal; and a fourth N-type doped region, a fifth N-type doped region, and a sixth N-type doped region formed in the P-type semiconductor region, wherein the fourth N-type doped region and the fifth N-type doped region are respectively formed on two opposite side of the P-type semiconductor region, which is directly arranged under the second word line, the fifth N-type doped region and the sixth N-type doped region are respectively formed on two opposite side of the P-type semiconductor region, which is directly arranged under the second common-voltage gate, and the fourth N-type doped region is coupled to the first select line. ### Claim 5 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is selected to perform a forming activity, the first common-voltage line is coupled to a middle voltage, the first word line is coupled to the middle voltage or a low voltage, and the first select line is coupled to a grounding voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 6 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is not selected to perform a forming activity, the first common-voltage line is coupled to a middle voltage, the first word line is coupled to a grounding voltage, and the first select line is coupled to a biasing voltage or electrically floating, the middle voltage is higher than the biasing voltage, and the biasing voltage is higher than the grounding voltage. ### Claim 7 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is selected to perform a setting activity, the first common-voltage line is coupled to a half of a middle voltage, the first word line is coupled to the middle voltage or a low voltage, and the first select line is coupled to a grounding voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 8 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is not selected to perform a setting activity, the first common-voltage line is coupled to a half of a middle voltage, the first word line is coupled to a grounding voltage, and the first select line is coupled to a biasing voltage or electrically floating, the middle voltage is higher than the biasing voltage, and the biasing voltage is higher than the grounding voltage. ### Claim 9 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is selected to perform a resetting activity, the first common-voltage line is coupled to a grounding voltage, the first word line is coupled to a middle voltage or a low voltage, and the first select line is coupled to a half of the middle voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 10 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is not selected to perform a resetting activity, the first common-voltage line, the first word line, and the first select line are coupled to a grounding voltage. ### Claim 11 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is selected to perform a reading activity, the first common-voltage line is coupled to a grounding voltage, the first word line is coupled to a middle voltage or a low voltage, and the first select line is coupled to a biasing voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the biasing voltage. ### Claim 12 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the first non-volatile memory cell is not selected to perform a reading activity, the first common-voltage line, the first word line, and the first select line are coupled to a grounding voltage. ### Claim 13 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is selected to perform a forming activity, the second common-voltage line is coupled to a middle voltage, the second word line is coupled to the middle voltage or a low voltage, and the first select line is coupled to a grounding voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 14 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is not selected to perform a forming activity, the second common-voltage line is coupled to a middle voltage, the second word line is coupled to a grounding voltage, and the first select line is coupled to a biasing voltage or electrically floating, the middle voltage is higher than the biasing voltage, and the biasing voltage is higher than the grounding voltage. ### Claim 15 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is selected to perform a setting activity, the second common-voltage line is coupled to a half of a middle voltage, the second word line is coupled to the middle voltage or a low voltage, and the first select line is coupled to a grounding voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 16 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is not selected to perform a setting activity, the second common-voltage line is coupled to a half of a middle voltage, the second word line is coupled to a grounding voltage, and the first select line is coupled to a biasing voltage or electrically floating, the middle voltage is higher than the biasing voltage, and the biasing voltage is higher than the grounding voltage. ### Claim 17 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is selected to perform a resetting activity, the second common-voltage line is coupled to a grounding voltage, the second word line is coupled to a middle voltage or a low voltage, and the first select line is coupled to a half of the middle voltage, the middle voltage is higher than the low voltage, and the middle voltage and the low voltage are higher than the grounding voltage. ### Claim 18 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is not selected to perform a resetting activity, the second common-voltage line, the second word line, and the first select line are coupled to a grounding voltage. ### Claim 19 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is selected to perform a reading activity, the second common-voltage line is coupled to a grounding voltage, the second word line is coupled to a middle voltage or a low voltage, and the first select line is coupled to a biasing voltage, the middle voltage is higher than the low voltage, the middle voltage and the low voltage are higher than the biasing voltage, and the biasing voltage is higher than the grounding voltage. ### Claim 20 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein when the second non-volatile memory cell is not selected to perform a reading activity, the second common-voltage line, the second word line, and the first select line are coupled to a grounding voltage. ### Claim 21 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein the P-type semiconductor region is a P-type semiconductor substrate. ### Claim 22 (depends on 4) The small-area common-voltage multi-write non-volatile memory array according to claim 4, wherein the P-type semiconductor region is a P-type doped well and the P-type doped well is formed in an N-type semiconductor substrate.