Memory cell with contiguous P-well and N-well structures

A method of operating a non-volatile memory cell comprising a body;

• a first well of a first conductivity type in the body;
• a second well of a second conductivity type in the body;
• the first and second wells being arranged adjacent and contiguous to each other, wherein the first conductivity type is P-type and the second conductivity type is N-type;
• a first conduction region, a second conduction region, and a third conduction region in the first well, the first, second, and third conduction regions being of the second conductivity type;
• a control gate region of the second conductivity type in the second well;
• a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor;
• a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element, the method comprising:
• a programming phase, comprising:
• turning on the selection transistor;
• bringing the storage transistor in a programming current conduction condition, and generating a programming electric field at the storage transistor;
• and
• an erasing phase by tunneling at the capacitive element, the erasing phase comprising:
• applying a first voltage between 10V and 16V to the control gate region, and
• applying a second voltage equal to 0V to the selection gate and to the first conduction region.

A method of operating a non-volatile memory cell comprising a body;

• a first well of a first conductivity type in the body;
• a second well of a second conductivity type in the body, the first and second wells being arranged adjacent and contiguous to each other, wherein the first conductivity type is P-type and the second conductivity type is N-type;
• a first conduction region, a second conduction region, and a third conduction region in the first well, the first, second, and third conduction regions being of the second conductivity type;
• a control gate region of the second conductivity type in the second well;
• a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor;
• a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element, wherein the control gate region is a single implanted region, the method comprising an erasing phase, the erasing phase comprising:
• applying a first voltage to the first well, and
• applying a second voltage to the second well, the second voltage being greater than the first voltage.