Memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChien Hui Huang, Kao-Cheng Lin, Wei Min Chan, Shang Lin Wu, Chia-Chi Hung, Wei-Cheng Wu, Chia-Che Chung, Pei-Yuan Li, Chien-Chen Lin, Yung-Ning Tu, Yen Lin Chung
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Abstract
A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.
Claims20
A memory device, comprising:
- a first memory cell comprising:
- a first transistor;
- and
- a second transistor coupled to the first transistor in parallel, wherein gates of the first transistor and the second transistor are coupled to each other,
- wherein an active area of the first transistor and an active area of the second transistor extend in a first direction and overlap with each other in a layout view, and the gates of the first transistor and the second transistor extend in a second direction to pass different layers and the active area of the first and second transistors, the second direction being different from the first direction, wherein types of the first transistor and the second transistor are a same.
A memory device, comprising:
- a first memory cell comprising:
- a first transistor comprising:
- a first terminal configured to receive a first bit line signal;
- and
- a first gate terminal configured to receive a first word line signal;
- a second transistor comprising:
- a second terminal configured to receive a second bit line signal;
- and
- a second gate terminal configured to receive a second word line signal, wherein the first gate terminal of the first transistor and the second gate terminal of the second transistor are located on different layers, and types of the first transistor and the second transistor are a same;
- a first multiplexer coupled to the first terminal of the first transistor and the second terminal of the second transistor, and configured to select a first voltage level stored in the first transistor or a second voltage level stored in the second transistor.
A memory device, comprising:
- a first memory cell comprising:
- at least two first transistors coupled to each other in parallel, wherein gates of the at least two first transistors are coupled to each other, and located on different layers,
- wherein active areas of the at least two first transistors overlap with each other in a layout view;
- and
- a second memory cell comprising:
- at least two second transistors coupled to each other in parallel, wherein gates of the at least two second transistors are located on different layers, wherein the gate of one of the at least two first transistors and the gate of one of the at least two second transistors are located on a same layer, and types of the at least two first transistors and the at least two second transistors are a same.
Dependencies are inferred from the claim text.